Lab

Lab 4 - ECE 421L

Author: David Silic

EE421L

prelab:

The Prelab deals with completing tutorial 2 from CMOSedu.com.

In this tutorial we learn how to simulate NMOS and PMOS transistor circuits and how to design the layout for NMOS and PMOS in cadence.

The completed layouts are pictured below:

Lab report:

Now that the tutorial is completed we move on to the main lob work.

To begin we simulate ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. A 6u/600n width-to-length ratio is used.

Schematic:

For this simulation we must use a parametric analysis and step VGS:

Which gives us the following graph:

Now we simulate ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.

This time VDS is fixed so the parametric step is not required:

Resulting Graph:

Now we do the same steps with our PMOS schematic:

First we simulate ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. We use a 12u/600n width-to-length ratio:

Once again we use a parametric analysis:

Which results in this graph:

Same as NMOS we now set VDS to 100mV and simulate ID v. VSG where VSG varies from 0 to 2 V in 1 mV steps.

Resulting in the following:

Now that our simulations are finished we move on to designing Laying out our NMOS and PMOS devices. First up we design a 6u/600u NMOS device connected with 4 MOSFET terminals to prob pads and run the corresponding DRC and LVS checks.

NMOS schematic.