Lab 2 - ECE 421L
Author: David Silic
Email: silic@unlv.nevada.edu
EE421L
After downloading the lab2.zip file and modifying the cds.lib file, I opened up the Sim_ideal_10-bit_DAC schematic which is shown below.
Now I launch the ADE L window and load the correct state in cellview:
I
get the following plot after running the simulation:
I want to make the graph more visible so I change the background color by right clicking anywhere on the graph and selecting graph properties and white background from the resulting menu. I can also edit the trace width by right-clicking on the traces and changing trace parameters from the trace properties
menu. This process yields the following plot:
2)
The previous plot shows an input voltage of 2.5 with an offset of 2.5 V.
This plot has a large number of small steps and the individual steps are hard to see. Thus I decreased the input voltage to 25mV which allows a clearer picture for each step. We not that the bottom step is the Least Significant Bit and represents the magnitude of the voltage step for each bit. Note the marker shows the bottom step has a magnitude of 4.88mV.
3)
From the above plot we have a simulated result of 4.88 mV for the LSB.
However we can calculate the LSB given VDD and the number of bits using the following formula:
In our case VDD = 5V and we have B[9:0] or 10 bits.
Thus:
Which
matches our simulated results.
Postlab:
10 bit DAC using n-well R of 10k:
How
to determine the output resistance of the DAC (answer:R)
by combining resistors in parallel and series:
The resistance of the DAC is fairly easy to calculate. The first set of resistors is simply 2R in parallel with 2R this simplifies to R, which in turn makes the next set of resistors to be 2R in parallel with 2R again. Solving in this way all the way up the DAC results in an Equivalent resistance of R.
Now I Ground all DAC inputs except B9, connect B9 to a pulse source and connect a 10pF load.
We note the Delay should be calculated by the equation td = 0.7RC
Given R = 10k and C = 10pF we calculate the following:
td = (0.7)*10k*10pF
Which equals approximately 70 ns
Simulation of delay:
Here a 1us delay is added for a clear view of the signal.
The initial marker at ½ the output voltage shows 1.0697 us, which when subtracted from the 1us offset, gives very close to 70 ns as predicted.
Now we create a symbol for our 10-bit DAC.
Here is the symbol imported into the ADC to DAC simulation.
Now we sim the above circuit to verify the operation of our new DAC design.:
We note the waveform looks the same and has 10 steps.
Now we add a a resistive load:
The Resistor will reduce the output voltage, basically acting like a voltage divider. We note that when a 10k load is used, like in the above simulation, the voltage will drop by half as the 10k equals the 10k equivalent of the DAC.
Now we add a capacitive load:
The capacitor smooths the output signal, reduces the voltage, and moves the phase angle forward by 90 degrees.
Finally we combine both the resistive and capacitive loads, which leads to a combination of the effects observed above: Both a lowered voltage and a smoothing/shifting.
We note that if the switch resistance is not small compared to R than it will combine with the 2R on the right side of each leg of the voltage divider, this will ultimately cause the final R to be lower, lowering the output.
As in lab 1 I saved my report both on my computer and on my Google drive account.
