Project - EE 421L Serial-to-parallel converter

Authored by Marco Muñiz

11/12/13

Email: munizm1@unlv.nevada.edu

Lab description:

For this Lab Project, we will draft and layout a Serial-To-Parallel Converter. This circuit will be given serial input date and will output an 8-Bit Word and Clock. In order to create this circuit, we must first draft the individual parts the make it up. First, we drafted a Transmission Gate which is a Voltage controlled switch made up of an NMOS and PMOS. Secondly, we used the created TG(Transmission Gate) to draft an Edge-Triggered D Flip-Flop. With the D Flip-Flop created, we were able to set a Shift-Register which was made up of 8 D Flip-Flops in series. This Shift-Register allows us to store 8 Serial Bits of Data. Lastly, the individual Shift-Register outputs were connected to the inputs of another set of 8 D Flip-Flops in series. However, this second set of D Flip-Flops is controlled by a Delayed Clock that is 8 times slower than the CLK_IN controlling the first set which will generate a 8-Bit Parallel when the clock is shifted to High. This Delayed Clock was created by Cascading 3 seperate D Flip-Flops with each one slowing the CLK_IN by Half of its original value. With 3 of these, we are able to achieve 1/8th of the original Input Signal. 

Transmission Gate:

Edge Triggered D Flip-Flop:

1/8th Delayed Clock:

Delayed Clock Simulation:

Shift Register:

 Serial-to-Parallel Converter:

Serial-to-Parallel Converter Simulation Examples:

For this Simulation, We used a serial date string of 11001100. We can see in the simulation that the outputed word is correct, with D0-1 outputting HIGH, D2-3 outputting LOW, D4-5 outputting HIGH, and D6-7 outputting LOW. 

For this Simulation, We used a serial date string of 11111111 . We can see in the simulation that the outputed word is correct, with D0-7 outputting HIGH. 

This Concludes the Schematic portion of the Lab Project. 

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PROJECT  

PART 2 : LAYOUT

For this part of the project, we will be laying out the mosfets for the various parts of the Serial-to-Parallel Converter. 

Below, we have the layout for the D Flip-Flop. Each of the layouts will consist of some arrangement of a number of these Flip-Flops. 

D FLIP-FLOP:  

Layout:

Extracted: 

DRC & LVS:

Once the D Flip-Flop is succesffuly layed out, we can proceed to the Delayed Clock Layout. This layout will consist of three D Flip-Flops with their D-In connected to Q_Bar and Q connected to the Clk_in of the next Flip-Flop. This makes the Flip-Flops act as dividers for the input CLK_IN signal. 

DELAYED CLOCK:

Layout: 

Zoomed in view (LEFT)

Zoomed in view (RIGHT)

Full View:

Extracted: 

DRC and LVS:

With the Delayed Clock complete, we now move on to the Shift Register Layout. 

SHIFT REGISTOR:

Layout:

Zoomed in view 

Full View:

Extracted:

DRC and LVS:

Once all of these layout are complete, we can now move on to the final layout for the Serial-to-Parallel Converter. This layout will conisist of all the previous layouts above. 

SERIAL-TO-PARALLEL CONVERTER:

Layout: 

Module View:

Extracted: 

DRC and LVS:

This concludes the projects for EE-421L Fall 18. 

This complete design directory can be found Here.

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