Authored by Marco Muniz,

11/5/18

email: munizm1@unlv.nevada.edu

Prelab:

For the Prelab, we will be working through Cadence Tutorial 5, This Tutororial will cover: the use of Array Lines(Busses), creating a Ring-Oscillator Schematic, the Simulation of the Ring-Oscillator, and lastly the Layout for the Ring-Oscillator.

 
Schematic & Sim:

 
Layout with LVS/DRC:

 
This concludes the end of the prelab.
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Lab:
 
STEP 1:
For the first part of the lab, we will be using the Concise Schematic of a 4-bit Inverter to run simulations for various capacitive loads. We must also describe how the different capacitive loads effect the Rise and Fall Times of the Outputs.
 
Concise Schematic & Symbol:
 
   
Simulation & Results:
 
 
In the above results, we can see that the added capacitive loads increase the Rise and Fall times compared to the output without and added capacitor.
 
STEP

For this step, we must create 8-bit I/O Array versions of the various logic gates used in this lab.
 
8-bit NOT Gate:
 

 
8-bit Nand Gate:


 
8-bit And Gate:


 
8-bit Xor Gate:


 
8-bit Nor Gate:


 
8-bit Or Gate:


 
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Step 3:
Run simulations for each Logic Gate to show that they work correctly.
 
The Schematic below was used to simulate the outputs of each logic gate, with and without a load attached.
 
Logic Gate Schematic:

 
Not Gate Results:

 
Nand Gate Results:

 
And Gate Results:

 
Xor Gate Results:

 
Nor Gate Results:

 
Or Gate Results:

 
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Step 4:
Simulate the given 2to1 MUX/DEMUX circuit and analyze the simulation results.

MUX/DEMUX circuit & Results:

 
MUX Results:


From the above results,
We can see that:

• When S is Inputing LOW, Z gives Input B
• When S is Inputing HIGH, Z gives Input A 

• When S is Inputing LOW, B outputs Z
• When S is Inputing HIGH, A outputs Z

Full Adder Simulation & Results:
 

Layout & Extracted:

 
Left Side of Layout:

 
Right Side of Layout:

 
Extracted:

DRC & LVS:

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Lab Back-up:

This Concludes Lab 7.

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