Lab 6 - EE 421L 

Authored by Marco Muniz,

Email: munizm1@unlv.nevada.edu

10/22/2018 

Prelab

For the Prelab, we followed the steps within tutorial 4 which went over designing CMOS Logic Gates. What we learned from this tutorial will be demonstrated throughout the lab. Specifically, the tutorial walks you through the design of a NAND gate. However since the NAND is also a part of the main lab, the NAND is placed in the main portion of the lab report. 

The Prelab also required that we back up our finished lab directory. This can be seen in the image below. 

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Lab 

Step 1: Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS). Create the layout and Symbol for all gates and show the final DRC and LVS with no errors. 

Below we can see the Complete Nand Gate Design.

SCHEMATIC:

SYMBOL:

LAYOUT With Completed LVS and DRC:

Once this is done, we move on to the Complete XOR Gate Design. 

 SCHEMATIC:

SYMBOL:

LAYOUT With Completed LVS and DRC:

The complete Schematics and Layouts for the above gates can be found in the lab6_mm.zip located at the bottom of this page.

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Step 2: Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11).

Gate Simlulation Schematic: 

Logic Gate Output Analysis along with gate Truth Table: 

Step 3: Using these gates, draft the schematic of the full adder. Create a symbol for this full-adder.

Simulate, using Spectre, the operation of the full-adder using this symbol. DRC and LVS your full adder design.

SCHEMATIC: 

SYMBOL:

LAYOUT With Completed LVS and DRC: 

As with the Logic Gate designs, the Complete Full-Adder Design can be found in the lab6_mm.zip folder at the end of the page.

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Step 4: Simulate, using Spectre, the operation of the full-adder using this symbol. 

Full-Adder Simulation Schematic:

Full-Adder Simulation Output and Logic Truth Table:

As with the Logic Gate Simulation, we can see a few glitchy moments between the Pulse changes. We can see in the images above, the Full-Adder operates as expected and follows the Truth Table Logic. 

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Design Directory Files can be found Here: lab6_mm.zip

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