Lab 3 - EE 421L 

Authored by Marco Muñiz

Email: munizm1@unlv.nevada.edu
09/17/2018 

Lab Description: 

    In this lab, we will be creating the layout for the 10-bit Digital-to-Analog Converter (DAC) that we designed in the previous lab. The layout will consist of stacked 10k n_well resistors and will show all metal 1 connections, as well as input and output pins.

Prelab: 

For the Prelab, we needed to finish the second half of the Cadence Tutorial 1. The first part of the tutorial covered the set up needed to use Cadence, such as the uploading of the various design kits and library files into our student directories. The last part of Tutorial 1 covered the creating and simulating of a voltage divider circuit, which we later created a symbol for so that we could easily use in future designs. From that point, we needed to create the layout for this resistive divider and upload our finished circuit. 

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1 
• Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS
• Use this n-well resistor in the layout of your DAC
• Discuss, in your lab report, how the width and length of the resistor are measured 
• Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
• All input and output Pins should be on metal 1
• DRC and LVS, with the extracted layout, your design (show the results in your lab report)
• Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

Part 1 

  For the first part, we will create the layout for a 10k Resistor using the n-well. However to do this, we must follow the MOSIS design rules set in-place. To begin this layout, we must calculate the Length and Width needed to achieve 10k Ohms of resistance. We will do this by using the equation....

Where,

R = Resistance needed (In Ohms)

Rsquare = Sheet Resistance of n-well (Set at 819/Per Sq.)

L = Length

W= Width

However, we must take into account the minimum requirements for the L and W. This value is set at 3.6 um. This value originates from the value of Lambda, given in the C5 processes, of 0.30 um. With this noted, we can decide on a value for the width (that is a multiple of Lambda=0.30um) and solve for the needed length. 

We will use a width of 4.5um for our 10k Resistor. With the width decided, we can calculate the needed length using the previous equation.

However, the calculated length doesn't fall within the needed multiple of Lambda so we will increase the length to 57um (or

190 Lambda).

Using these values, we can then layout our 10K n-well Resistor and run the DRC to see if we are meeting the needed design rules.

 Part 2

 For the final part, we will now layout the 10-bit DAC using the 10k n-well resistor created in the previous part. 

Above, we can see the completed layout for out 10-bit DAC. When laying the 10k n-wells out, we need to note that the C5 Process sets the minimum spacing between well's to 5.4um. To account for this, we placed each well 5.7um from each other to not run into unneeded pain. 

Next,

We then ran all the needed rule checks to make sure that our design accounted for all design rules and specs. We ran the DRC to check our n-well's for any sizing or spacing issues. 

Lastly, after extracting the finished DAC layout, we ran the LVS to check for any abnormal pin issues between our layouts and schematics. Both checks run through with no errors or warnings so we are clear.  

In the above results, we can see that our LVS ran through with no Netlist issues. We are now finished with our 10-bit DAC Layout!

Finally, we upload our finished "Lab 3" Library for back-up purposes. 

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