Lab 1 - ECE 421L 

Author:    Nicholas Mingura,

Email:      mingura@unlv.nevada.edu

08/30/2018 

  

Lab description

In this lab the goal was to make a voltage divider using Cadence Viruoso in the ON C5.

 

Pre-lab

For the first part of the prelab it is directed to upload a snip of the snip instructions.

 http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab1/snip1.JPG

Image 1: Picture of the snip instructions in the prelab.

   

For the second part of the prelab it was instructed to input a table into the webpage and add numbers to the rows and columns.

   

451651565115186
5416985181651681
841621328465175

   

Lab:

   

For this lab the main goal was to set up our individual cadence accounts in order to use the virtuoso command. This involved editing through the libraries as shown to us in our lab instructions as well as learning the commands on the consol. After getting the libraries set up we change directories to CMOSedu using the cd CMOSedu comand, and then using the command virtuoso & bring up our library manager as well as letting us to continue using the window with the &.

   

http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab1/Cadence_CD_Snip.JPG

Image 2: Starting screen of cadence showing directory change and viruoso command.

   

After launching the library manager a new library was created for lab one, which also had a cellview and schematic made for it as well. In the schematic view the task was to make a voltage divider with a 1V dc supply and two 10k ohm resistors. After selecting all the comonents they were connected with wire using the w command, then the wires were labeled with the l command. 

   

http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab1/Voltage_Div_Schematic.JPG

Image 3: Finished voltage divider schematic with labeled wires.

   

After making the schematic the ADE window was opened and needed to have input a transient analysis for 1 second. Then The wires labled in and out were selected to be ploted for the transient analysis, showing that out is half the voltage of in.

   

http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab1/ADE_State.JPG

Image 4: ADE window and settings for simulation.

   

http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab1/Voltage_Div_Simulation.JPG

Image 5: Simulation of Voltage divider showing out is half the voltage of in.

   

All of the files of this lab were zipped up and are in a folder on the desktop and in Google drive.

http://cmosedu.com/jbaker/courses/ee421L/f18/students/mingura/lab%201/Backup.JPG

Image 6: Zipped file on desktop and Google drive

   

   

   

   

   

   

Return to Nicholas Mingura's Labs

Return to EE 421L Labs