Lab 2 - ECE 421L
Email:
loreto@unlv.nevada.edu
Prelab
DAC schematic.
DAC waveform simulations.
These waveforms can be further studied by changing the input voltage to better see the steps indicated in the output voltage. By setting the voltage to 10 mV with an offset of 10 mV, the steps can be better observed.
How is Vin related to B[9:0] and Vout?
-B[9:0] is the 10-bit representation of Vin.
-The ADC takes the analog input from Vin and converts it to a 10-bit digital output: B[9:0]
-The DAC takes the 10-bit digital signal from B[9:0] and converts it back to analog, a smooth continuous waveform, for Vout.
How to Determine the Least Significant Bit (LSB)
1 LSB=VDD/2^N =5V/2^10 =5V/1024= 4.88 mV
Lab 2 Report:
-How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and series.
We analyze the resistor networks at each of the bits individually. For example, on B0, we have a 2R in parallel with another 2R. Finding the equivalent resistance of that section yields R. This new R is then added in series with the R in the network for B1, creating another 2R//2R network, thus making the equivalent resistance for B0 and B1 = R. This process is repeated all the way up through B9, in which it is proven that the equivalent resistance for the entire DAC = R.
-Delay, driving a load.
By using the mathematics from above, we can determine that the equivalent resistance of the DAC = 10k. We can use this to predict the time delay of the circuit when it drives a 10pF load. Hand calculations result in the time delay = 70 ns.
t_d=0.7RC=0.7(10*〖10〗^3 Ω)(10*〖10〗^(-12) F)=7*〖10〗^(-8) s = 70 ns
DAC schematic and supporting simulation:
td = 569 ns - 500 ns = 69 ns
-How to create a symbol view for your design with the exact same footprint as the Ideal_10-bit_DAC symbol view
By using the cell Ideal_10-bit_DAC as a reference, the task is to create my own 10-bit DAC to test in the overall circuit.
I start by creating a voltage divider schematic to represent the connections between the 2R and R resistors for each bit branch. By clicking Create -> Cellview -> From cellview, I make the symbol for the voltage divider to create the DAC with.
We then create a new schematic in the Mydesign_10-bit_DAC file, in which the newly created voltage divider symbol is used. By cascading 10 of them together, 1 per bit, the DAC design is replicated. The schematic and the symbol created from it are shown below.
- Simulations to verify your design functions correctly.
After copying the files from sim_Ideal_ADC_DAC to cell sim2_Ideal_ADC_DAC, we switch out the ideal DAC in that file with the DAC we just created.
I kept getting errors when running the simulation, which prevented a full time sweep, but from what was shown, the input and output voltages are replicated nearly identically when there is no load.
We now add a 10k resistive load and simulate. When the 10k load is added, the output voltage is reduced to half of the input voltage. The input voltage oscillates from 0-5 V, and the output voltage oscillates from 0-2.5V.
Next, we add a 10pf capacitive load and simulate. The capacitor gives an offset voltage of 1V, causing the output voltage to oscillate between 1 and 4 V.
- In a real circuit, the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). Discuss what happens if the resistance of the switches isn't small compared to R.
If the switch resistance in the circuit isn't as small compared to R, it would affect the equivalent resistance of the entire DAC. Different calculations will need to be made on the resistance for the DAC to properly match the load and get the most optimal output.