Lab 4 - ECE 421L 

Authored by Michael Loreto,

Email: loreto@unlv.nevada.edu

September 26, 2018 

This lab analyzes the IV characteristics and layouts of the NMOS and PMOS devices using the C5 process.

Prelab work:

Go through Tutorial 2:

NMOS data from Tutorial 2:

Inner Schematic
Symbol
Layout
Extracted
Simulation Schematic
Simulation Curves

PMOS data from Tutorial 2:

Inner Schematic
Symbol
Layout
Extracted
Simulation Schematic
Simulation Curves

• Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):

Description	Schematics	Simulations
A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.

• Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads. (Including DRC check and LVS) 

Schematic
Layout
Extracted
DRC
LVS

• Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. (Including DRC check and LVS)

Schematic
Layout
Extracted
DRC
LVS

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