Lab 3 - ECE 421L
Email:
loreto@unlv.nevada.edu
Prelab
This lab makes use of the n-well resistor design to create a layout of the DAC from Lab 2. The procedure starts by creating the actual n-well resistor, and then implementing it into a layout file for the DAC as per instructions. DRC and LVS are run to ensure the design functions properly.
Finish through Tutorial 1.
In the last part of Tutorial 1, I edit the schematic for R_div, I use my 10k n-well resistor to create a layout of the same R_div, and extract it. I run the DRC and LVS to ensure that all three match up.
Upon running the LVS after creating all three files shown above, the job successfully completes, and it indicates that the netlists for all three files match up.
Lab 3 Report:
-Use the n-well to layout a 10k resistor as discussed in Tutorial 1.
The layout and extracted files for the n-well 10k resistor are shown above. The new value for the extracted resistor is 10.21 k.
-Discuss in your lab report, how to select the width and length of the resistor by referencing the process the process information from MOSIS.
R = Rsquare * (Length / Width)
According to MOSIS, Rsquare for n-type resistors = 819. Using this along with the minimum design width of 4.5 microns, the length needed for the resistor can be calculated as such:
10k = 819 * (Length / 4.5u) --> Length = approx. 56 um
-Use this n-well resistor in the layout of your DAC
-Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
-All input and output Pins should be on metal 1
Above is the entire layout of the DAC using 31 n-well resistors. The connections between the layout resistors are made with the metal1 layer.
I have provided a zoomed image of the B9, B8, and Vout pins to better show the pin layouts and the connections for the design. I connect two 10k resistors in series to replicate the 2K resistors in the original schematic, and connect those in parallel to the R resistors as needed.
-DRC and LVS, with the extracted layout, your design
There were 0 errors in my DAC layout upon running the DRC.
The LVC was able to run to completion, however, despite several attempts to change the layout design to try and fix this, the net-lists failed to match.
Zipped up Lab files: Click Here