Project - ECE 421L 

Authored by Brian Medrano Kiaer

November 13, 2018

kiaer@unlv.nevada.edu

Project Description: 

Design a serial-to-parallel converter that takes serial input data and an associated clock signal and generates an 8-bit output (parallel) word and clock. 

• The inputs will be Din and clock_in 
• The outputs will be D0-D7 and clock_out
• If the serial input is 10Mbits/s then the parallel output is 1.25 MWords/s. 

Inverter:

Here is one of the components needed for the the Serial to Parallel converter. This is a 6u/6u Inverter used for the D Flip Flop mentioned later on this page. The layout view and extracted view are also displayed below. The layout was created using a Standard cell in order to have an organized layout with other components needed.

     

 






Transmission Gate:

Here is the schematc and symbol for the Transmission Gate using a 6u/6u PMOS and NMOS. This component is also used to implement a D Flip Flop.

    

Below displays the layout (left) and the extracted view (right) of the Transmission Gate with verification of DRC and LVS.

 







D Flip Flop:

The D Flip Flop schematic is below which uses 4 6u/6u Inverters and 4 Transmission Gates (TG). In the schematic, a 5th inverter is used to simulate an invertered clock signal. The symbol is also show below, using a triangle to indicate the CLK signal.



  

Layout:



Extracted:



DRC


LVS



D FlipFlop Simulation:













CLK_OUT:

I created a symbol to simulate Clock_out which would act as clk/8. I used three D Flip Flops to simualte clock/2^N with N as the number of D Flip Flops.

Layout:

LVS

CLOCK/8 OUTPUT SIMULATION:

8-bit Serial-to-Parallel Converter: 

Here is the final schematic used for the 8-bit Serial-to-Parallel Converter. This schematic uses two main registers the Shift Register and the Hold Register shown below. The Shift Register uses the normal clock input while the Hold Register uses clock_out which in this case is clock/8. The input is connected to the CLK_OUT symbol above to implementthe effects of clock_out. Lastly, I created a symbol that has two inputs (Din and clk) and nine outputs (D0-D7 and CLK_OUT).

Shift Register: 

Full Shift Register Layout (click to zoom):

Hold Register: 

Schematic:

Full Hold Register Layout: (click to zoom)


Below shows examples of the outputs on the hold register: CLK_OUT and D7 (circled in red)

 

Full Schematic: 

Full Layout of 8-bit Serial-to-Parallel Converter: (click to zoom)

LVS

Simulations:

Here is the output waveform of the above schematic above. For this simulation the output I am aiming for is to get 11110000. 

When looking at the waveform output D0-D7 the results are 11110000 at 0.8  us. 

Here is a second simulation using a serial input for Din to get an output of 10110011. When creating the input Din is inputted as 11001101. 

When looking at the output from D0-D7 the output is as expected at 0.8us 10110011.

Here is a third simulation using a serial input for Din to get an output of 10010101. When creating the input Din is inputted backwards as 10101001. 

When looking at the output from D0-D7 the output is as expected at 0.8us 10010101. 

My Design Directory is here: LAB_PROJECT.zip 

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