Lab 7 - ECE 421L
For the prelab we are required to go through Tutorial 5 which corresponds to creating a design, a layout, and a simulation of a ring oscillator.
This is the schematic for the ring oscillator within Tutorial 5. Above the inverter symbol where it states "I0<1:31>" that is stating that this is a 31 stage ring oscillator. A wide wire is added to act as a bus for the multiple signals of the ring oscillator.
Then I created the layout of the 31 stage ring oscillator. I first instantiated the layout used previously for one inverter and then created connections and copied that layout 30 more times to a matched layout to the schematic.
Next, I performed a simulation on a cellview called "sim_ring_osc" and used the extracted view to ensure that the outcome was the same as 31 inverters in series.
I ensured that the layout passed the DRC verification.
I also ensured that the layout, extracted view, and schematic passes the LVS verification.
Here is the schematic I used for the simulation above. This schematic uses the symbol from the ring_osc cellview and I added a 5V vdc so the Stimuli was not necessary. I also added an initial condition to the output "osc_out" at 0V using Simulation->Convergence Aids->Initial Condition..
Here is to verify that the extracted view is working the way it is supposed to.
LAB WORK:
1) Create a 4-bit Inverter
I simulated the results with the capacitive loads indicated in Lab 7. My obervation of the waveforms below show that when a larger load capacitance is added the longer the delay will be. For example, we can see that the output waveform out<1> has the largest capacitor at 1pF and also has the longest delay as well.
2.) Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
8-bit NAND GATE:
Simulation schematic and respective waveforms:
8-bit NOR GATE:
8-bit NOR Gate schematic and symbol
Simulation schematic for 8-bit NOR gate and respective waveforms
8-bit AND GATE:
8-bit AND gate and symbol
8-bit INVERTER:
8-bit Inverter schematic and symbol
8-bit OR GATE:
8-bit OR Gate schematic and symbol
Simulation schematic for 8-bit OR Gate and respective waveforms
3) Create a 2-to-1 MUX/DEMUX
The multiplexer/demux works by turning on a specific TG at a time. For example below, when S is high the output Z is B and when Si is high (S is low) the output Z is equal to A.
One FA showing metal3 connection to second FA
DRC Verification for 8-bit Full Adder.
LVS verification of 8-bit Full Adder
My design directory can be found here: Lab7.zip