Project - EE 421L Serial-to-Parallel Converter
Authored
by Biruk Gebremeskel
Email: gebreb1@unlv.nevada.edu
November 14, 2018
Lab
description:
The purpose of this lab is to design a serial-to-parallel converter
that takes serial input data and an associated clock signal and
generate an 8-bit parallel output(word) and a clock.
Inverter Schematic and Symbol
Transmission gate(T-gate) Schematic and Symbol
Edge Triggered D-flip flop Schematic and Symbol
Edge Triggered D-flip flop Simulation
Shift Register Schematic and Simulation
Serial-to-Parallel Converter Schematic, Symbol, and Simulations
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This simulation was tested using the 8-bit binary number 01010101, and it shows in the simulation.
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The second simulation is tested using an 8-bit binary number 00001111 as it shows in the simulation.
The third simulation is tested using an 8-bit binary number 00110011 as it shows in the simulation below.
Layout,Extracted, DRC, and LVS of the D-Flip Flop and Serial to parallel Converter
D-FF layout
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D-FF Extracted
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DRC
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LVS
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Serial to Parallel Converter Layout
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Serial to Parallel Converter Extracted
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Closer but partial views of the layout and Extracted
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Serial to Parallel Converter DRC
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Serial to Parallel Converter LVS
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All my Cedence schematics, simulations, layouts, etc can be downloaded in the link below.
Proj_BG_F18
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