Final Project - ECE 421L
Authored
by Jovanne Dahan
dahanj1@unlv.nevada.edu
November 13,
2018
Post-lab:
The first cellview I made was for the inverter.
I used this inverter for the D flip-flop schematic and to make the clock
transitions sharper.
Next, I made the schematic and symbol for a D flip-flop. Eight of these D
flip-flop will be used to make the serial to parallel converter.
My serial to parallel converter is as shown below. It takes in a serial
input and the most recent 8-bits will be outputted as D<7:0>, where
D<7> is the most recent bit and D<0> is 8th bit before
that.
Simulations:
The schematic below is what I used for the following waveforms. The only
element I changed for each waveform is Din.
In the simulation below I let Din be an arbitrary pulse. From the output
we can see that the serial to parallel converter is positive edge triggered
because the outputs are only taking the inputs during the positive edge of the
clock. If it was negative edge triggered the output would be 8’b01001010.
In the waveform below I used an input of 8’b00000111 (in the waveform we
have to read it from right to left because the leftmost part of the waveform is
the oldest). The parallel output matches the serial input, where D7 is the most
significant bit and D0 is the least significant bit.
In this simulation I used another arbitrary input. The result is as
expected: where D7 is the most recent input and D0 is the input from 8 cycles
before D7.
·
Layouts
Single DFF
Layout
Buffer Layout
These buffers are here to ensure that the rise and fall times are quick.
Clock Divider
Layout
The clock divider below slows down the clock by a magnitude of 8.
Full Layout
for the Serial to Parallel Converter
Below we see where the elements in the schematic correspond to the
layout.
Project file: proj.zip