Lab 7 - ECE 421L
Authored
by Jovanne Dahan
dahanj1@unlv.nevada.edu
November 11,
2018
Post-lab:
·
4-bit Inverter
In order to create the 4-bit inverter seen below, I instantiated a 6u/6u
inverter and set its name to I0<3:0>. Then I just had to make sure the
input and output buses were also 4-bit wide. The resulting symbol I created for
that inverter is the one seen below. Below we can see that we are using wires
to pick which output bit we want to operate on. When a capacitor is connected
as a load to the output, the rise and fall time of the output voltage are
drastically altered.
·
8-bit NAND
Similar to the 4-bit inverter, I simply instantiated a 1-bit NAND gate
and renamed it as I0<7:0> to signify that there are 8 NAND gates. Each
bit of the word A and B will be operated on by their respective NAND gate.
·
8-bit NOR
The schematic I used for a 1-bit NOR gate is as seen below. From this
schematic I created a symbol, which is shown in the following image (the one
with my initials). The next steps I took is the same from the 8-bit NAND gate.
·
8-bit AND
For the 8-bit AND gate I used the NAND gate with an inverter connected to
the output. I had to make sure that I specified for there to be eight inverters
for the schematic to check and save.
·
8-bit Inverter
The steps I took to draft the 8-bit inverter was the same as the 4-bit
inverter. Nothing interesting.
·
8-bit OR
Similar to the AND gate: I connected an 8-bit inverter to the output of
the 8-bit NOR gate to create and 8-bit OR.
·
Simulation of the Gates
This first simulation shows the operation of the gates for input
combinations A=8’b1, B=8’b1 and A=0, B=0. All the gates are operating as
expected, proven by the waveforms. I also only looked at the first bits of the
outputs.
The second simulation uses inputs A=1, B=1 and A=0, B=0. This is
different from the previous pairs of inputs because these ones do not specify
the specific bit. Therefore, it assumes all 8 bits of the word to be 1 for the
first pair and zero for the second.
The last simulation uses the input pairs A=1, B=0 and A=0, B=1. The gates
still function correctly but there are spikes during the rise and fall times.
·
2-to-1 MUX/DEMUX Schematic and Symbol
I used the images in the Lab 7
page as a reference to draft the schematic shown below.
1. 2-to-1 MUX
Simulation
In this simulation we have A=1 and B=0. Select is a logic “1” on the
first half-cycle and logic “0” on the other. In the waveform below we can see
that Out = A when S (select) is “1” and Out = B when S is “0”.
2. 2-to-1 DEMUX
Simulation
In the following DEMUX simulation I allowed z to be logic “1”. When S=1 A
becomes “1” and when S=0 B becomes “1”. When either of them are not logic “1”
we can see from the waveforms that they increase in voltage. In that state they
are in highZ mode because there is no load connected
to them.
·
8-bit MUX/DEMUX
Like with the previous 8-bit gates, I renamed the MUX to I0<7:0> to
signify that there are 8 of them. I also connected an 8-bit inverter from S to
Si so that we would only require one input for the select.
1. 8-bit
MUX/DEMUX Simulations
The first simulation is a simple one: A=1, B=0 and S alternates between
“0” and “1”. From the waveform we can conclude that when select is “0” Z=B; and
when select is “1” Z=A. This is no different from the 1-bit MUX/DEMUX.
For the second simulation let A=8’b00011111 and B=8’b00000000 (with the
same select input as the previous simulation). From the waveform below we can
see that when select is “1” – that is, Z=A – the output is also 8’b00011111.
·
1-bit Full Adder
For the schematic I simply followed figure 12.20. I used 6u/.6u for the
NMOS and PMOS and 6u/6u for the inverter.
·
8-bit Full Adder
Using the symbol from the 1-bit full adder, I renamed it with
I0<7:0> to make it an 8-bit full adder. The schematic and symbol is shown
below.
1. 8-bit Full Adder Simulations
For the simulation I decided to add A=4 + B=3. I did so by letting A<7:3>=0,
A<2>=1, and A<1:0>=0 for A=8’b00000100. For B, I let B<7:2>=0
and B<1:0>=1 in order for be to equal 8’b00000011. The simulation shows
that the output S=8’b00000111=7, which is the expected value.
2. Layout and DRC
In order to make the layout for the 8-bit full adder, I first made a
layout for the 1-bit adder (seen below). After that I
was able to DRC and LVS that layout I instantiated eight of them to make the
8-bit full adder. I had to rename all the As and Bs to their corresponding bit. Then I connected the Cn+1 to
the Cn of the next full adder (and the last Cn+1 connects to the first Cn).
3. LVS
Zipped folder
for Lab
7