Lab 4 - ECE 421L
Authored
by Jovanne Dahan
dahanj1@unlv.nevada.edu
25 September
2018
Post-lab:
·
ID v. VDS Curves for NMOS
Following the instructions, I set VDS=0 and VGS=VGS, and (although not shown
here) VBS=gnd. Launching ADEL and following the rest of the instructions
resulted in the I-V curves shown below. As expected, the curves follow expected
NMOS I-V curves.
·
ID v. VGS Curves for NMOS
Using Ch6_IC61 Fig6_19_NMOS_ID_VGS as a reference, I connected node B to
the negative terminal of VSB resulting in the schematic below. At first I
believed the I-V curves to be inaccurate because they do not look like the
exponential curves that I expected. However, this is due to the fact that VGS
varies from 0 to 2V, which is a large range compared to the Fig 6.19’s 500mV.
·
ID v. VSD Curves for PMOS
Below is an image of my PMOS circuit with the body connected to Vdd = 5V.
·
ID v. VGS Curves for PMOS
Again, I used Ch6_IC61 Fig6_19_PMOS_ID_VSG as a reference for generating
the ID v. VGS curves. In my circuit, VBS is connected to the body of the PMOS.
By varying the voltage of VBS from 0 to 1 in five steps, the waveforms below
are generated.
·
NMOS Device
Creating the layout for the NMOS with the terminals connected to probe
pads was difficult at first. Firstly, I had to figure out that metal1 connects to metal2 using the via layer and metal2
to metal3 using via2. Then, I had to make sure that the pads were 30um apart from
each other and the metal2s; also,
that the metal3s were 0.9um apart.
After completing all those checks, I obtained the layout shown below.
After many attempts the design rule check of the layout resulted in no
errors as seen below.
Below, the images for the extracted view and the schematic used for LVS
are shown.
The LVS resulted in a matching net-list between the extracted view of the
layout and the schematic.
·
PMOS Device
Creating the layout for the PMOS was a lot easier because I learned from
all my failures laying out the NMOS.
The DRC shows no errors were found.
The dimensions of the extracted view of the layout and the schematic
match: a good start to an LVS job.
The LVS job for the PMOS shows that the net-list match.
