Lab 3 - ECE 421L
Authored
by Jovanne Dahan
dahanj1@unlv.nevada.edu
18 September
2018
Post-lab:
Layout view of my 10k resistor.
Extracted view of my 10k resistor
·
Selecting width and length
First, you
have to apply the equation
.
For an
n-well resistor, the sheet resistance is about 800Ω/square, and we want R
to equal 10kΩ. After you plug those numbers in you will find that l =
12.5w. Next, you will find a value for w and l using this relationship. That
being said, the layout will have to follow SCMOS rules. Two of the most basic
rules that apply to n-wells is that the width has to be at least 3.6um and the
edges have to be on grid. The grid points are .15um apart, meaning the width
and length have to be divisible by .15um.
The full layout view of my DAC
Top and bottom view for my DAC
The DRC shows there are no errors in my layout.
Close up view of the extracted layout.
Performing the LVS between the extracted layout and schematic shows no
errors, as seen below.
Link to my cadence file for this project: lab3.zip