Lab 1 - ECE 421L

Layout and Simulation of a Resistive Voltage Divider 

Authored by Shadden Abdalla

abdals1@unlv.nevada.edu

8/30/18

Lab description:

In this lab, I created and simulated a resistive voltage divider schematic using Cadence Virtuoso in the ON’s C5 process using the MOSIS SCMOS design rules.

Pre-lab:

I created a CMOSedu account and edited my webpage, seen below.

Lab:

1. Set up Cadence using MobaXterm.

Create library: Tutorial_1 and then define it in the cdslib.

Below is the definition.

Create R_div schematic by instantiating two 10k resistors, a gnd, and a DC voltage source. I also added two wire labels and labeled both “in” and “out.”

I launched the ADE L and set up the circuit on a transient analysis of 1 second. Then I clicked on the wire labels that I wanted to plot and plotted “in” and “out.”

I saved the state into the cellview as “spectre_state1” before running the analysis.

Then I pressed the green play button in the ADE L to view the output. I changed the background color and lines.

Then I zipped up and saved the file.

I clicked on Tutorial_1 in the MobaXterm page (Cadence start window) and downladed it to my desktop into the 421lab1 folder.

Below is an image of the downloaded Tutorial_1 folder as well as the zipped up version of the same folder, seen diagonal to the Tutorial_1 original downloaded folder.

Then I put the zipped up file into the google drive and backed it up.

Return to Shadden’s 421L labs

Return to 421L Students