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Project: Design, layout, and simulation of an Even Parity Checker - EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 11/21/17
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Project description:
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Project Design:
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The objective of this project is to design an even parity checking circuit that has a 9-bit input, 8-bits data and 1-bit parity. This circuit should output a 1 when the even parity check is valid, and output 0 when the parity check is invalid |
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Using a group of NOR gates it is possible to create a parity generating circuit. Which will output a 1 when there is an odd number of 1’s in a sequence. |
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8-bit Parity Generating circuit |
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Link to download the zip file of my Cadence simulations, layouts, and schematics: EE421L_Project |
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8-Bit Parity Checker Symbol |
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8-Bit Parity Checker Schematic |
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2-input XOR schematic |
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2-input XOR Symbol |
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Even Parity Checker Schematic and Simulation 1 |
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Buffer Schematic |
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From the Parity Generating circuit we can compare that output with a Parity input using an XOR gate and Inverter that will output a valid or invalid check depending on the sequence of numbers placed on the input. |
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Even Parity Checker Schematic and Simulation 2 |
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8-Bit Parity Checker Truth Table |
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The first simulation we will test the number 11011100 on the input which has an ODD number of 1’s, so we expect a valid check when Parity is 1, and that is what we see in the simulation. |
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For the second simulation we will test the number 11111100 on the input which has an EVEN number of 1’s, so we expect a valid check when Parity is 0, and that is what we see in the simulation. |
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P |
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P |
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Check |
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Check |
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When implementing the Parity Checker it is important to add a Buffer in order to connect it to a Bond pad and be able to drive the signal off chip. |
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Buffer Symbol |
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*Note “EVEN” or “ODD” refers to the number of 1’s |
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Layout and Extracted Views |
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The layout of the even parity checker has been done so using the method of standard cell frames. |
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Layout of XOR gate used in the Parity Checker |
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Layout of Buffer used in the Parity Checker |
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Layout of Parity Checker |
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Extracted view of Parity Checker |
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Parity Checker DRC and LVS |
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Parity Checker Extracted simulation Schematic |
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Parity Checker Extracted simulation |
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P |
PGen |
Check |
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0 (EVEN) |
0 (EVEN) |
1 (VALID) |
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0 (EVEN) |
1 (ODD) |
0 (INVALID) |
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1 (ODD) |
0 (EVEN) |
0 (INVALID) |
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1 (ODD) |
1 (ODD) |
1 (VALID) |