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Lab 7: Using buses and arrays in the design of word inverters, muxes, and high speed adders - EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 11/08/17
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Pre-lab:
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Lab description:
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Experimental Results:
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· Back-up all of your work form the lab and the course. · Read through this entire lab write-up before doing the pre-lab · Finish Tutorial 5 |
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The objective of this lab is to design, layout, and simulate CMOS word inverter, MUX/DEMUX, and High speed adder |
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Exercise #1 - 2 – 4Bit Word Inverter
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4Bit Word Inverter Schematic |
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Exercise #2 - 8-Bit input/output array of NAND, NOR, AND, OR, and Inverter Gates
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Link to download the zip file of my Cadence simulations, layouts, and schematics: Lab7_MV |
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Exercise #3 - Design and Simulation of 2-1 MUX/DEMUX
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4Bit Word Inverter Simulation |
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8-Bit NAND Gate Schematic |
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8-Bit NAND Gate Symbol |
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2-1 MUX/DEMUX Schematic |
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8-Bit NOR Gate Schematic |
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8-Bit NOR Gate Symbol |
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8-Bit AND Gate Schematic |
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8-Bit AND Gate Symbol |
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8-Bit OR Gate Schematic |
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8-Bit OR Gate Symbol |
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8-Bit Inverter Gate Schematic |
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8-Bit Inverter Gate Symbol |
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8-Bit Logic gates Schematic |
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8-Bit Logic gates Simulation |
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2-1 MUX/DEMUX Simulation |
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2-1 MUX/DEMUX Truth table |
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Exercise #4 - Design and Simulation of 8-Bit 2-1 MUX/DEMUX with a single select line
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2-1 MUX/DEMUX Schematic with a single select |
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2-1 MUX/DEMUX Symbol with a single select |
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8-Bit 2-1 MUX/DEMUX Schematic with a single select |
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8-Bit 2-1 MUX/DEMUX Schematic with a single select |
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8-Bit 2-1 MUX/DEMUX Simulation |
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Exercise #5 - Design, layout, and Simulation of 8-Bit AOI Full adder
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AOI Full Adder Schematic |
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AOI Full Adder Symbol |
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8-Bit AOI Full Adder Schematic |
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8-Bit AOI Full Adder Symbol |
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8-Bit AOI Full Adder Simulation |
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For the Word inverter the delay increased as the capacitive load increased. Additionally, The wave forms became less and less square as the capacitive load increased affecting the rise and fall time by making them longer. |
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The 2-Bit DEMUX/MUX works by using two transmission gates with opposite inputs on each, so when the selector is high only one gate will be on. This allows the selection of two different data paths with one input. From the simulation you can see that the selector input determines which input is going to the output. The circuit can be used as both a MUX and DEMUX depending on which side is the input. |
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This 8-Bit full adder was tested by adding the number 11100000 from input A to 00001111 from input B. The result should be 11101111 Which can be seen on the simulation. |
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AOI Full Adder Layout and extracted view |
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AOI Full Adder DRC and LVS |
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8-Bit AOI Full Adder Layout and Extracted view |
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8-Bit AOI Full Adder DRC and LVS |
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