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Lab 6: Design, layout, and simulation of a CMOS NAND gate, XOR gate and Full Adder - EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 10/25/17
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Pre-lab:
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Lab description:
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Experimental Results:
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· Back-up all of your work form the lab and the course. · Read through this entire lab write-up before doing the pre-lab · Finish Tutorial 4 |
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The objective of this lab is to design, layout, and simulate a CMOS NAND gate, XOR gate, and Full Adder using ON’s C5 process |
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Exercise #1 - 2 – input NAND gate using 6u/.06u MOSFETs
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2-input NAND Schematic |
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Exercise #2 - 2-input XOR gate using 6u/0.6u MOSFETs
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Link to download the zip file of my Cadence simulations, layouts, and schematics: Lab6_MV |
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2-input NAND Layout |
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Exercise #3 - Simulation of NAND gate, XOR gate, and Inverter
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Exercise #4 - Full Adder
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2-input NAND LVS and DRC |
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2-input NAND symbol |
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2-input XOR schematic |
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2-input XOR Layout |
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2-input XOR Symbol |
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2-input XOR LVS and DRC |
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NAND gate, XOR gate, and Inverter Schematic |
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NAND gate, XOR gate, and Inverter Simulation |
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Truth table for NAND gate and XOR gate |
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Full Adder Schematic |
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Full Adder Layout |
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Full Adder LVS and DRC |
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Full Adder Simulation |
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Full Adder Truth table |
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A |
B |
A nand B |
A xor B |
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0 |
0 |
1 |
1 |
|
0 |
1 |
1 |
0 |
|
1 |
0 |
1 |
0 |
|
1 |
1 |
0 |
1 |
|
A |
B |
Cin |
S |
Cout |
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0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |