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Lab 4: IV Characteristics and Layout of NMOS and PMOS- EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 09/27/17
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Pre-lab:
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Lab description:
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Experimental Results:
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· Back-up all of your work form the lab and the course. · Read through this entire lab write-up before doing the pre-lab · Finish Tutorial 2 |
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The objective of this lab is to simulate the IV characteristics for both the NMOS and PMOS devices. Additionally, layout each device and connect the terminals to probe pads. |
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Exercise #1 - ID vs VDS of an NMOS device
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ID vs VDS Schematic: NMOS W = 6u, L = 600n
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Exercise #2 - ID vs VGS of an NMOS device
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DRC results shown in the command interpreter window |
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LVS results shown in the command interpreter window |
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Link to download the zip file of my Cadence simulations, layouts, and schematics: EE421L_Lab_4 |
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ID vs VDS Simulation: VGS 0v to 5V
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ID vs VGS Schematic: NMOS W = 6u, L = 600n
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ID vs VGS Simulation: VGS= 0v to 2V, VDS= 100mV
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Exercise #3 - ID vs VSD of a PMOS device
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ID vs VSD Schematic: PMOS W = 12u, L = 600n
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ID vs VSD Simulation: VSG= 0v to 5V
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Exercise #4 - ID vs VSG of a PMOS device
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ID vs VSG Schematic: PMOS W = 12u, L = 600n
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ID vs VSG Simulation: VSG= 0v to 2V, VSD= 100mV
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Exercise #5 - Layout of NMOS device with probe pads
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Layout of 6u/.6u NMOS device |
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Schematic of NMOS device with probe pad pins |
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Layout of NMOS with probe pads |
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Exercise #6 - Layout of PMOS device with probe pads
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Layout of 12u/.6u PMOS device |
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Schematic of PMOS device with probe pad pins |
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Layout of PMOS with probe pads |
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DRC results shown in the command interpreter window |
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LVS results shown in the command interpreter window |