|
Lab 3: Layout of 10-bit digital to analog converter (DAC) - EE 421L Author: Mario Verduzco Email: Verdum1@unlv.nevada.edu 09/20/17
|
|
Pre-lab:
|
|
Lab description:
|
|
Experimental Results:
|
|
· Back-up all of your work form the lab and the course. · Read through this entire lab write-up before doing the pre-lab · Finish Tutorial 1 |
|
The objective of this lab is to layout the 10-bit DAC from the previous lab. |
|
Exercise #1 - Use the n-well to layout a 10k resistor
|
|
10-bit DAC using 10k resistors |
|
Exercise #2 - Use the n-well resistor in the layout of the DAC
|
|
Layout of 10k Resistor using the n-well |
|
10k resistor extracted view |
|
The sizes chosen for this resistor are based on the process information from MOSIS and ON Semiconductor. |
|
Portion of DAC laid out using 10k resistors |
|
The same size resistor was used from the previous exercise. A minimum spacing of 5.4um was chosen. Also, following the lab guide all resistors must be laid out in parallel using the same x coordinates. |
|
DRC results shown in the command interpreter window |
|
LVS results shown in the command interpreter window |
|
Schematic of Ideal ADC with extracted DAC |
|
Simulation of Ideal ADC with extracted DAC |
|
Link to download the zip file of my Cadence simulations, layouts, and schematics: EE421L_Lab_3 |