Lab 07 - EE 421L 

Authored by Ethan Tash,

tash@unlv.nevada.edu 

11/08/2017 

 
Prelab:
 

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Fig 00: Backed up coursework
 

Postlab:
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Fig 01: Inverter schematic		fig%20inverter%20symbol.PNG







Fig 02: Inverter schematic
 
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Fig 03: 4-bit Inverter schematic
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Fig 04: 4-bit Inverter symbol
 
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Fig 05: Schematic of 4-bit inverter circuit for simulation of  load capacitance effects: C0=100fF, C1=500fF, C2=1pF 
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Fig 06: Simulation of  4-bit inverter circuit with load capacitance effects: C0=100fF, C1=500fF, C2=1pF 
 
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Fig 07: Schematic of 4-bit inverter circuit for simulation of  load capacitance effects: C0=500nF, C1=100nF, C2=1nF 
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Fig 08: Simulation of  4-bit inverter circuit with load capacitance effects: C0=500nF, C1=100nF, C2=1nF 
 
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Fig 09: Schematic of 4-bit inverter circuit for simulation of  load capacitance effects: C0=500uF, C1=100uF, C2=1uF
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Fig 10: Simulation of  4-bit inverter circuit with load capacitance effects: C0=500uF, C1=100uF, C2=1uF 
 
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Fig 11: 8-bit Inverter schematic
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Fig 12: 8-bit Inverter symbol
 
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Fig 13: Schematic of  8-bit inverter circuit with load capacitance effects: C0=500fF, C1=100fF, C2=1fF, C3=500pF, C4=100pF, C5=1pF, C6=500nF, C7=100nF
fig%208-bit%20inverter%20sim%203.PNG
Fig 14: Simulation of  8-bit inverter circuit with load capacitance effects: C0=500fF, C1=100fF, C2=1fF, C3=500pF, C4=100pF, C5=1pF, C6=500nF, C7=100nF
 
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Fig 15: 8-bit NAND schematic
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Fig 16: 8-bit NAND symbol
 
 

 
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Fig 21: MUX_2_1 Schematic                                                                                                        Fig 22: MUX_2_1 Symbol
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fig 23: MUX_2_1 Simulation A=0, B=1, Si=0, S=1
 
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fig 24: MUX_2_1 Simulation A=1, B=0, Si=0, S=1
 
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fig 25: MUX_2_1 Simulation A=1, B=0, Si=1, S=0
 
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fig 26: MUX_2_1 Simulation A=1, B=1, Si=0, S=1
 
The MUX is able to output Z regrdless of the operation of the inputs but is dependent on the values of S and S'



 

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