Lab 03 - EE 421L 

Authored by Ethan Tash,

tash@unlv.nevada.edu 

09/20/2017 

  

Prelab:
 
For the purpose of the pre lab I initially backed up all work related to the lab 2 which contained files related to the Ideal 10-bit ADC to DAC circuit in my CMOSedu library.
Following cadence tutorial 1 
 
Postlab:
 
Below are the documents used to begin design with, which give us our values of lambda and also the parameters we must stay in for values to be divisible by so that cadence will recognize them as within the MOSIS standard. The calculations for verifying our values for the n-well resistor as previously used in other homework is also figured in the report.
 
 
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Fig 0: illustrates the link provided on the course website to the design rules
 
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 Fig 1: this is a table containing the actual design rules that we will be utilizing in both the lecture and the lab

  

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Fig 2: additional design rules for 0.60 micrometers is provided along with links to more comprehensive documentation

 

As part of previous homework assignments we did calculations for a set lambda in relation to our individual designs. below are those calculations verifying 

our design is within standards as the boarder is at 56.1 from edge to edge running the length of the nwell.

 

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Fig 3: are the calculations verifying the design is in compliance with MOSIS design standards

  

The N-well resistor and the 10-bit DAC realized with 10k resistors:

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Fig 4: the n-well resistor designed within MOSIS standards using the bind key 'k' you can set a ruler or just modify within properties

 

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Fig 5-7: is the schematic layout for my 10-bit DAC using 10K resistors representing 2R and R from the previous lab

 

N-well layer for the construction of the 10-bit DAC realized with 10k n-well resistor:

 

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Fig 8-10: is the view of my nwell layer with the viewing set to 0 which shows only component outline

 

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Fig 11-12: is the view of my nwell layer with the viewing set to 10

 

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Fig 13: this is the extracted view of my nwell layer confirming equal resistance for each nwell resistor 

  

Final Result: The LVS showed successful netlist matching 

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Fig 14: the confirmation of successful DRC verification and LVS 

 

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Fig 15: is from the LVS output text file showing that my netlist did indeed match

  

 Click to Download lab 3 zip file

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