| The
Even bit Parity checker's output "check" is true when inputs D0-D7 and
P are equal to an even number of 1's. For example should the D0-D7 have 5 1's then the P should be 1 to make the number of 1's even. If the P is 1 then the output should be 1 showing the parity is correct, but if the P is 0 then the output is zero to show there is an error. This is done by using XOR gates to check if the inputs are different then Inverting the last XOR output. If the output was left noninverted we would instead be checking for errors in the parity bit. | ||
Inverter: | ||
Inverter Schematic: | Inverter symbol: | Inverter Layout: |
Xor:The exclusive or gates output is 1 only if the number of input 1's is odd. | ||
Xor Schematic: | Xor Symbol: | Xor Layout: |
Simulation for both Inverter and Xor: | ||
Parity Checker: | ||
Schematic for the parity checker: | ||
Simulation schematic: | The Schematic to the left is using semi random input values. Most of the pulses are two times faster than the previous pulse to show more possible cases. | |
output waveform: | ||
layout of even parity checker:  (click for zoom) The top four xor gates corespond to the first four gates using D0-D7 the second four xor gates are the three gates connecting everything together and one xor for the Parity in The last gate is the inverter that connects to the buffered pad frame. | ||
Layout without the buffer: | ||
DRC results: | LVS results: | |
Simulation of extracted view for the parity checker: | ||