Lab X - EE 421L 

Authored by Angel Solis, Solisa1@unlv.nevada.edu

Today's date :  11/4/2017

 PreLab:

Ring Oscillator schematic:
Ring_OSC output wave:
Ring_OSC Layout:
DRC results:
LVS Results:
Symbol waveform:
Extracted Waveform:
 

Post Lab:

 

4X Inverter: 

Inverter 4x Schematic:

Inverter 4x symbol:

Simulation Schematic:
Simulation Wave:

As the capacitive load increases the delay also increases.
 
 

8X Inverter: 

Inverter 8x Schematic:

Inverter 8x symbol:

Simulation Schematic:

Simulation Wave:

  
 

8X AND: 

AND 8x Schematic:

AND 8x symbol:

Simulation Schematic:

The waveform to the right shows that the output is only true when both inputs are true.
Simulation Wave:

  
 

8X NAND: 

NAND 8x Schematic:

NAND 8x symbol:

Simulation Schematic:

The waveform to the right shows that the output is only low when both inputs are true.
Simulation Wave:

  
 

8X NOR: 

NOR 8x Schematic:

NOR 8x symbol:

Simulation Schematic:

The waveform to the right shows that the output is only true when both inputs are false.
Simulation Wave:

  
 

8X OR: 

OR 8x Schematic:

OR 8x symbol:

Simulation Schematic:

The waveform to the right shows that the output is only false when both inputs are false.
Simulation Wave:

  
 

2to1 MUX: 

2to1 MUX Schematic:

2to1 MUX symbol:

  The Above multiplexer/ demux works by only turning on one set of TGs at one time. This means that either A is connected to Z or B is connected to Z. This connection goes both ways meaning that A to Z and Z to A are both usable.
 

8X 2to1 MUX: 

2to1 MUX 8x Schematic:

2to1 MUX 8x symbol:

Simulation Schematic:

Simulation Wave:

Demux 8x Simulation Schematic:
Waveform for Demux:
  
 

8X FullAdder: 

Simulation Schematic:


FA 8x wave:
FA 8X zoomed in layout:
FA 8X Layout:
FA 8X Extracted:
DRC Results:
LVS Results:
 
lab7.zip

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