Lab 6 - EE 421L 

Authored by Angel Solis, Solisa1@unlv.nevada.edu

Today's date :  10/10/17

  

Prelab:

schematic for the NAND gate:

 


Symbol for the NAND gate:

Schematic for simulating the NAND gate:


Waveform for the above simulation:

Laout for the NAND gate:

DRC results for the NAND gate:

LVS results for the nand gate:

Post Lab:
   
Standard cell used for layout:

 
NAND Gate:
NAND Schematic:
NAND Symbol:

NAND Layout:
NAND DRC results:

 
 
 
 
 
 
LVS results:

 

Xor Gate:
Schematic:
Symbol:
Layout:
DRC results:
LVS results:
 
 
Gate Simulations:

Schematic:

Simulation Wave:

Extracted Simulation:

The small glitches seen when A and B both change are caued by the fact that both will be around halfway on for a small amount of time. This causes the output to take both as being on but only for a small amount of time.
 
 
Full Adder:
Schematic:

Symbol:

Simulation schematic:

Output Wave:

Layout View:

Extracted View:

DRC results:


LVS results:
Extracted Simulation Wave:

 

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