Lab 5 - EE 421L 

Authored by Angel Solis, Solisa1@unlv.nevada.edu

Today's date : 9/25/17

  

Pre Lab:

    Tutorial 3 Questions: 


1.     What does the Bindkey q do?
                q opens up the property menu for the selected item.

2.    Which two Cell Views are used when doing an LVS?
            extracted and schematic

3.    What is the difference between the nmos and nmos4 schematic cells?
        nmos has 3 terminals body is grounded and the nmos4 has all 4 terminals

4.    How do you select the MOSFET models in the ADE window? What does ADE stand for?
            ADE: Analog Design Enviorment, setup -> model library -> (...) Select the files at /ncsu-cdk-1.6/models/spectre/standalone/ami06n and p.

5.    What is the difference between moving and stretching?
            moving is used to pick up and relocate an object
            streaching is used to deform and streach the object from one side.

6.    How do you layout a rectangle on the metal1 layer?
        ensure that metal1 draw layer is selected and hit r and begin drawing the rectangle.

7.    What does the ! indicate at the end of gnd! and vdd!
         the ! means that the net is global

8.    What do the acronyms LSW and CIW stand for?
           LSW: Layout Selection Window
           CIW: Command Interpreter Window

9.    How is the ruler used? Cleared?

        The ruler is used by pressing k and clicking on the starting and ending locations.
        The ruler is cleared by pressing Shift+K

The inverter is setup as shown using a Pmos connected to VDD and an Nmos connected to gnd.

Below is the symbol view for the above circuit. 


This is the layout setup for the same inverter:

This shows the extracted view which in turn shows that the Nmos and Pmos were created correctly.


Below are the LVS results for the inverter:


The DC response is shown below for the inverter when VDD is not present.


This is the DC responce for the inverter when VDD is present and set to 5V:


Below is the same simulation but this time using the extracted layout version of the inverter:

Lab description:

Below is the schematic View for a 12u/6u Pmos to Nmos ratio inverter:

 This is the symbol created for the inverter:

Below is the schematic View for a 48u/6u Pmos to Nmos ratio inverter using a multiplier of 4:

 This is the symbol created for the inverter 48/24 u inverter:

This is the layout for the 12/6 u inverter:

This shows the DRC results for the 12/6 inverter:

This is the extracted view showing that the pmos and nmos are created correctly.


This shows the LVS results for the Extracted and Schematic of the 12/6 u inverter:

This is the layout for the 48/24u inverter:

DRC results for the above layout:

LVS results for the 48/24 u inverter:

Below is the extracted view that shows that the transistors are layed out correctly:


This is the setup for the spice simulation of the inverter with a capacitive load.


ADE setup for the 12/6 inverter with a capacitive load:


The waveform for all 4 capacitors are show below:


below is the capacitive load for the 48/24 u inverter:


This shows the ADE settings used for the 48/24 u inverter:


This is the waveform for all 4 capacitive loads:


This is the ultra sim results for the 12/6u inverter:


This is the ultra sim waveform results for the 48/24u inverter:

Link to lab5_AJS.zip

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