Lab

Lab 4- EE 421L

Authored by Angel Solis, Solisa1@unlv.nevada.edu

Today's date : 9/20/17

Prelab:

During tutorial 2 we set up the following nmos:

Creating a symbol for it we get the following:

Setting up the IV output we get the following schematic:

Using the parameters specified in the tutorial we get the following output wave:

The extracted view shows that the layout was setup correctly:

Running LVS on our layout and schematic we get the following:

Doing the same for a PMOS we get the following layout:

setting up the schematic for the IV curve we get:

This is the output wave generated:

This is the LVS results for the PMOS:

Lab description:
ID v. VDS of an NMOS with a 6u/600n width-to-length ratio waveform and schematic:

ID v. VGS of an NMOS with a 6u/600n width-to-length ratio waveform and schematic:

ID v. VSD of an PMOS with a 12u/600n width-to-length ratio waveform and schematic:

ID v. VSG of an PMOS with a 12u/600n width-to-length ratio waveform and schematic:

Layout of a 6u/0.6u NMOS with all terminals connected to probe pads:

DRC results for the NMOS:

LVS results for the NMOS:

Schematic used for the LVS with the NMOS:

Layout of a 12u/0.6u PMOS with all terminals connected to probe pads:

PMOS DRC results:

PMOS LVS results:

Schematic used for the LVS with the PMOS:

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