Lab Project - ECE 421L

Authored by Brett Smith (smithb25@unlv.nevada.edu)

Tuesday, November 14th, 2017

Updated Tuesday, November 21st, 2017

In this lab I designed the schematic for an 8-bit even parity checker. Originally I spent a lot of time trying to design a single 9 input device using AOI gates and it just never seemed to like it was going to produce a layout with fewer gates than individual XOR gates, maybe if I could reasonably do a 5 dimensional Karnaugh map I could find a lower total gate count, but for this schematic I went with 7 XOR's to find the parity of the data and an XOR combined with an inverter to form an XNOR to compare the parity input with the data's actual parity.

The first thing I did was copy over my trusty inverter design. I have been using this exact design for several labs now, and am very confident in its behaviour, but just for posterity sake I simulated it using stimuli within the ADE so an external simulation schematic was unnecessary.

Inverter schematic

Inverter symbol

Inverter simulation results

Now that I can reliably invert signals I drafted an XOR based on figure 12.18 from the book. I used 20/10 size MOSFETs to keep the switching point consistent. Again I simulated this schematic using ADE stimuli.

XOR schematic

XOR symbol

XOR simulation results

With all the building blocks in place it was time to draft the parity checker. This is not exactly rocket science. I think this is a schematic straight from the CPE 200 textbook. Each indiviual XOR gate evaluates if an odd or even number of 1's are present at it's inputs. If it's an even number the output is 0 and if it's an odd number the output is a 1. This behaviour allows a cascade of XOR gates to be used because a 1 can only be output if one input represents an odd number of 1's and the other input represents an even number of 1's. In any other condition the total number of 1's will be even and the output will be a 0. The final gate is an XOR followed by an inverter forming an XNOR or equivelance gate that will test to make sure the ouput of the XOR cascade is the same as the parity input.

To keep this schematic reusable I chose to create a sim schematic that can handle the global vdd! net. I used stimuli to vary the inputs over the whole range of 512 possible inputs. I inspected several sections and am convinced that it is working properly. I included a small snippet of those results so that it's legible. The inverter on the output is 48/96 size so that when the p input is the only input that changes the rise time with no load will be something like:

.7*20kΩ/48*[2.5fF(6+12)(.6)^2+3/2*2.5fF(48+96)(.6)^2]+.7*40kΩ/96*2.5fF(48+96)(.6)^2 = 99ps

And with a 10pF load the rise time with no load will be something like:

.7*20kΩ/48*[2.5fF(6+12)(.6)^2+3/2*2.5fF(48+96)(.6)^2]+.7*40kΩ/96*[2.5fF(48+96)(.6)^2 + 10pF] = 3.0ns

Parity checker schematic
Parity checker symbol	Parity checker simulation schematic
Parity checker simulation results

Now that the I have a theoretical design it's time to figure out how to layout all 98 gates in an area somewhat smaller than a pepperoni pizza.

Step 1 was to layout a standard XOR gate. Using standard-cells and a little bit of space between the PMOS and NMOS devices I was able to layout the two inverters and the 8 MOSFETs in an XOR in a pretty tight and compact area. This layout DRC'ed and LVS'ed with very few issues.

XOR layout

XOR extracted

XOR DRC XOR LVS

With a trusty standard XOR gate in hand it was time to layout the whole kitten kaboodle. I had commited to vertical traces on the metal1 layer and horizontal traces on the metal2 layer. Because all of the space between the MOSFETS on metal2 was already occupied I had to connect the XOR gates together with traces on metal2 that run over the top of the MOSFETs. Because these traces are orthagonal to almost all of the traces below them hopefully this shouldn't be an issue. To make sure the output inverter fits reasonably well within this layout I decided to use the same widths as the other MOSFETs and gain the additional driving capacity with a x8 multiplier. I also greatly increased the trace size on the output to ensure it can handle the larger current flow. This whole contraption fits nicely within a 400μm x 40μm layout area so I'm pretty happy with that. Simulating the extracted view of the layout shows similar results to the schematic simulation so it's quite possible that this design might actually work when it's fabicated on a die.

Parity checker layout

Parity checker extracted

Parity checker DRC Parity checker LVS

Parity checker extracted simulation results

As a final sanity check I simulated the delay time through the extracted layout with and without the load. With no load the delay was around 690ps. That's 7 times slower than I calculated. I'm not really sure where this error came from, but atleast it's in the right order of magnitude I guess. With the 10pF load the delay was close to 2ns which is 33% faster than I calculated. This error is more like what I would normally expect. What this does illistrate is that the output buffer is large enough to drive an off chip load provided the signal stays comfortably below 100 MHz. I would imagine there are other more limiting factors that will prevent this design from achieving this speed.

Parity checker delay with no load

Parity checker delay with 10pF load

It sure seems that this parity checker design is complete. It'll be interesting to see this fabricated to see how it works.

The library for my design can be downloaded here. Both my lab and this website have been backed up.

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