Lab 8 - ECE 421L

Authored by:

    Brett Smith (smithb25@unlv.nevada.edu)

    Aaron Nicolas Escobedo (escoba3@unlv.nevada.edu)

    Trevor Ensign (ensigt1@unlv.nevada.edu)

Tuesday, December 5th, 2017

 

Chip design library for this project: Chip2_f17

 

For the final lab we were asked to compile a design for a chip to be fabricated. Specifically, the devices to be on the chip are:

• One, or more if possible, course projects (A parity checker)
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider
• A 25k resistor implemented using the n-well
• Whatever else you would like to fabricate to use the remaining pins on the chip

We chose to add two of our SMPS designs from the lecture project to our chip, and that fills up our 40 pins. We chose to lay our chip out using the following chip assignments:

We assembled our chip design and drafted the following schematic and layout:

Schematic

Layout

Here are the details of how to use each device on our chip:

 

Parity Checker:

Device Usage Pin # Description 6 D0 Input 5 D1 Input 4 D2 Input 3 D3 Input 2 D4 Input 1 D5 Input 40 D6 input 39 D7 Input 38 Parity Input 37 Check Output 36 Vdd Input 20 Ground This even parity checking circuit will output a 1 on the check output when the parity input matches the parity of the input word and will output a 0 when it doesn't match. Pin 36 is connected to the Vdd ESD ring. Only the parity checker is powered by it, but connecting this to Vdd will protect other inputs from high voltage transients.

Ring Oscillator:

Device Usage Pin # Description 31 Vdd Input 35 Ring Oscillator Output 20 Ground The oscillator will produce a clock signal whenever Vdd and ground are applied with no other stimuli.

NAND Gate:

Device Usage Pin # Description 23 Vdd 24 A Input 25 B Input 26 A NAND B Output 20 Ground

NOR Gate:

Device Usage Pin # Description 27 Vdd 28 A Input 29 B Input 30 A NOR B Output 20 Ground

Inverter:

Device Usage Pin # Description 32 Vdd 33 A Input 34 A NOT Output 20 Ground

PMOS Device:

Device Usage Pin # Description 13 Drain/Source 14 Gate 15 Source/Drain 16 Body

NMOS Device:

Device Usage Pin # Description 17 Drain/Source 18 Gate 19 Source/Drain NOTE: Body connected to pin 20

Resistor Divider:

Device Usage Pin # Description 20 25kΩ resistor 21 25kΩ & 10kΩ resistors connected 22 10kΩ resistor Resistors form a voltage divider if Vdd is applied to pin 22 and ground is connected to pin 20.

SMPS1:

Device Usage Pin # Description 10 Vout Output 11 Voltage Feedback Input 12 Vdd 20 Ground This is Brett's SMPS design. It requires a .5mH inductor connected between Vout and Vfb and a 1.5uF capacitor connected between Vfb and ground. When connected thos way 3.75V @ up to 100mA output will be produced at the node connected to Vfb.

SMPS2:

Device Usage Pin # Description 7 Vout Output 8 Voltage Feedback Input 9 Vdd 20 Ground This is Trevor's SMPS design. It requires a 160uH inductor connected between Vout and Vfb and a 220nF capacitor connected between Vfb and ground. When connected thos way 3.75V @ up to 100mA output will be produced at the node connected to Vfb.

The chip DRCs and LVSs and should work as designed once it is fabricated. All data for this project has been backed up in our shared Google Drive folder.

Schematic

Layout

 

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