Lab 4 - ECE 421L

Authored by Brett Smith (smithb25@unlv.nevada.edu)

Tuesday, September 27th, 2017

 

In this lab I drafted an NMOS and a PMOS MOSFET and performed a few simulations on them. To begin with I created copies of the NCSU nmos and pmos cells and performed various simulation to create baseline ID curves.

 

NMOS ID Schematic
NMOS ID test schematic
PMOS ID Schematic
PMOS ID test schematic
ID v. VDS of an NMOS device
ID v. VDS of an NMOS device with Vgate varying from 0 to 5V
ID v. VSD of a PMOS device
ID v. VSD of a PMOS device with VSG varying from 0 to 5V

ID v. VGS of an NMOS device
ID v. VGS of an NMOS device with VDS = 100 mV and Vgate varying from 0 to 2V
ID v. VGS of an NMOS device
ID v. VSG of a PMOS device with VSD = 100 mV and VSG varying from 0 to 2V
 

After I had the basic performance of the devices I placed probe pads on the layout and modified the schematic to match. As you can see on the right I eventually got both design to pass both DRC and LVS.

  


NMOS layout
Layout of my NMOS MOSFET with probe pads

NMOS layout zoomed
Layout zoomed in to see NMOS device
NMOS layout schematic
NMOS device schematic

NMOS DRC passed
DRC passed

LVS passed
LVS passed
 

PMOS layout
Layout of my PMOS MOSFET with probe pads

PMOS layout zoomed
Layout zoomed in to see PMOS device
PMOS layout schematic
PMOS device schematic

PMOS DRC passed
DRC passed

LVS passed
LVS passed
 

Now that my devices could be probed after manufacturing I redid my simulations to ensure that performance had not changed. Below you can see the simulation results that look identical to the previous simulations.

 

NMOS ID Schematic
My extracted NMOS ID simulation schematic
PMOS ID Schematic
My extracted PMOS ID simulation schematic
ID v. VDS of an NMOS device
ID v. VDS of an NMOS device with VGS varying from 0 to 5V
ID v. VSD of a PMOS device
ID v. VSD of a PMOS device with VSG varying from 0 to 5V

ID v. VGS of an NMOS device
ID v. VGS of an NMOS device with VDS = 100 mV and VGS varying from 0 to 2V
ID v. VGS of an NMOS device
ID v. VSG of a PMOS device with VSD = 100 mV and VSG varying from 0 to 2V

 

The library for my design can be downloaded here. 

 

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