Lab 7 - EE 421L
Authored
by Andy Sam,
sama1@unlv.nevada.edu
11/8/2017
In
lab 7, we use busses and arrays to design multi-bit inverters, logic gates, muxes, and adders.
Word Inverter Schematic:
Word Inverter Simulation results:
As
we can see from the simulation, a stronger capacitance tied to the
output of the inverter creates a longer delay in both the rising and
falling edges. This creates a less sharp edge, which is something we
would want to avoid.
NAND gate schematic:
8 Bit NAND gate array schematic:
NOR gate schematic:
8 bit NOR gate array schematic:
AND gate schematic (inverted NAND):
8 Bit AND gate array schematic:
OR gate schematic (inverted NOR):
8 Bit OR gate array schematic:
Schematic for all logic gate arrays:
Simulation for all logic gate arrays:
2-to-1 Mux schematic:
8 bit 2-to-1 MUX array schematic:
8 bit 2-to-1 MUX array simulation:
:
As
we can see, when the select bit is 0, the output of the mux matches the
input of A. When the select bit is 1, the mux matches the input of B.
If we swapped the output MUX_out to an input, and A and B to outputs,
we could easily have a DEMUX where the select bit will output MUX_out
to either A or B. Based on the transistor design, this works because if
A is selected (S = 0), the the PMOS and NMOS of A turn on and allow the
signal from MUX_out to flow to A. B will be 0 no matter what, as both
the MOSFETs are off. If S = 1, the same thing applies to B but
vice versa. The signal to A would be zero because its MOSFETs are off.
Full Adder Schematic:
8 bit Full Adder schematic:
8 bit Full Adder simulation results:
Because
we kept A and B the same signals for all 8 bits, every sum output will
be the same, but we can notice how the carry out bit changes when an
overflow occurs. We can also notice the increasing delay between the
sum output bits around the 100 ns mark. This is because the later
stages of the adder have to wait for the signals from the earlier
stages of the adder before doing their operation.
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