LAB 7 - EE 421L
Prachi Patel
patelp3@unlv.nevada.edu
PRELAB:
I updated files to Google Drive.
The ring oscillator created is as shown below in the lab. I used the same one and changed the size from <0:30> to <0:4>.
LAB:
The following 4-bit inverter uses bus wire to create an array of
4-inverters. I turned that schematic into a symbol of x4 inverter and
then simulated it using three different capacitors and pulsing voltage
source.
![1](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_4_sc.png)
![2](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_4_sym.png)
![3](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_4_sim.png)
![4](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_4_wf.png)
INVERTER, NAND, NOR, OR and AND Gates
The NAND and Inverter were already created
previously so I used the symbols to create a 8-bit ring-oscillator. For
NOR, OR and AND, I used the schematics developed below to create 1-bit
symbols and then created the 8-bit ones.
![5](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_8_sc.png)
![6](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/inv_8_sym.png)
![7](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nand_8_sc.png)
![9](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nand_8_sym.png)
![12](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nor_sc.png)
![13](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nor_sym.png)
![10](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nor_8_sc.png)
![11](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/nor_8_sym.png)
![1](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/or_sc.png)
![1](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/or_sym.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/or_8_sc.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/or_8_sym.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/and_8_sc.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/and_sc.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/and_8_sym.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/and_sym.png)
For simulations, I used an example from one of the previous labs and
simulated them all at once using capacitors of load 100f, 500f, and 1p
F.
![s](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/gate_sim.png)
![s](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/gate_wf.png)
Next, I used the given schematic to create MUX/DEMUX.
Here, A B and Z are inputoutput while Si, S are inputs. This way, the
schematic can work as MUX and DEMUX by changing sources and loads.
![1](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/md_sc.png)
![2](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/md_sym.png)
The following are simulations for MUX, where A, B and S are inputs.
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/mux_sc.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/mux_sim.png)
This is the simulation for DEMUX where Z and S are inputs.
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/demux_sc.png)
![d](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/demux_sim.png)
The following simulation is for Mux, using 8-bit MUX.
![g](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/mux_8_sc.png)
![f](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/mux_8_sim.png)
This simulation is for Demux, using 8-bit MUX/DEMUX.
![3](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/demux_8_sc.png)
![f](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/demux_8_sim.png)
Next, I creates AOI Full Adder schematic using the book. Instead of
symbols like inverter, I used PMOS and NMOS to better figure out the
layout later.
Next, I converter the schematic into a symbol and then layout. The
following images include schematic, symbol, layout, DRC, extracted and
LVS of the AOI Full Adder.
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_sc.png)
![v](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_sym.png)
![d](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_layout.png)
![s](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_drc.png)
![d](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_ext.png)
![s](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_lvs.png)
This is similar to above, except it's an 8-bit AOI Full Adder. The following includes Schematic, Symbol, Layout, DRC and LVS.
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_8_sc.png)
![d](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_8_sym.png)
![a](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_8_lvs.png)
![z](http://cmosedu.com/jbaker/courses/ee421L/f17/students/patelp3/Lab%207/lab7/fa_lvs.png)