EE 421L

Lab 4  


Authored by Jeremy Morgan

Email: morgaj7@unlv.nevada.edu

Due: 9/27/2017


Pre-lab:

Back-up all of your work from the lab and the course.
Go Through Tutorial 2

Lab:
   
Part 1: Generating 4 Schematics with Simulations for NMOS and PMOS Analysis)

   
1. 
  
lab%204%20images/Schematic%20nmos.JPGlab%204%20images/NMOS%20GRAPH1.JPG
     
To Simulate this Layout, Used a linear step size while also using a parametric analysis. That gives us the 6 values.

Linear Step ADL :

lab%204%20images/TRANS%201.JPG
Parametric Analysis:

lab%204%20images/nmos%20parametric%20page.JPG
  
2. 

lab%204%20images/NMOS%20SCHEMATIC%202.JPG lab%204%20images/2%20GRAPH.JPG

Analog Design Environment:

lab%204%20images/2%20TRANS.JPG
     

3. 

lab%204%20images/3%20SCHEMATIC.JPG   lab%204%20images/3%20GRAPH.JPG
 
To Simulate this Layout, Used a linear step size while also using a parametric analysis. That gives us the 6 values.

Linear Step ADL :

lab%204%20images/3%20TRANS.JPG
Parametric Analysis:

lab%204%20images/3%20PARAMETRIC.JPG
  
4. 

    
lab%204%20images/3%20SCHEMATIC.JPGlab%204%20images/4%20GRAPH.JPG

Analog Design Environment:

lab%204%20images/4%20TRANS.JPG
    
Part 2
: Lay out a 6u/0.6u NMOS and PMOS device and connect all 4 MOSFET terminals to probe pads)
 
Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads.

NMOS Device:

lab%204%20images/5%20NMOS%20ZOOM.JPG

Connecting to Probe Pads:

Full Layout View:                                                                    Extracted Layout View:
lab%204%20images/5%20CONSTRUCTED%204%20PIN%20NMOS.JPG
        lab%204%20images/5%20EXTRACTED.JPG

Layout Passing DRC:

lab%204%20images/5%20NMOS%20DRC%20CONFIRMED.JPG
lab%204%20images/5%20DRC.JPG

Schematic to be Compared with Layout Using LVS:

lab%204%20images/5%20symbol%20view.JPG    

LVS Between Schematic and Layout: LVS shows both match

lab%204%20images/5%20FINAL%20LVS.JPG
   
Lay out a 6u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads

PMOS Device:

lab%204%20images/6%20PMOS%20ZOOMED%20IN%20LAYOUT.JPG

Connecting to Probe Pads:

Full Layout View:                                                                    Extracted Layout View:

lab%204%20images/6%20PMOS%20LAYOUT%20FULL%20VIEW.JPG       
lab%204%20images/6%20PMOS%20EXTRACTED%20FULL%20VIEW.JPG 

Layout Passing DRC:

lab%204%20images/5%20DRC.JPG

Schematic to be Compared with Layout Using LVS:

lab%204%20images/6%20PMOS%20SCHEMATIC%20VIEW%20FULL.JPG
   

LVS Between Schematic and Layout: LVS shows both match

lab%204%20images/6%20LVS%20FINAL.JPG

Lab 4 Files: HERE
    

Return to EE 421L Labs