EE 421L
Lab 4
Authored
by Jeremy Morgan
Email: morgaj7@unlv.nevada.edu
Due: 9/27/2017
Pre-lab:
Back-up all of your work from the lab and the course.
Go Through Tutorial 2
Lab:
Part 1: Generating 4 Schematics with Simulations for NMOS and PMOS Analysis)
1.
- A schematic for simulating ID
v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps
while VDS varies from 0 to 5 V in 1 mV steps. Using a 6u/600n
width-to-length ratio.
![lab%204%20images/Schematic%20nmos.JPG](lab%204%20images/Schematic%20nmos.JPG)
![lab%204%20images/NMOS%20GRAPH1.JPG](lab%204%20images/NMOS%20GRAPH1.JPG)
To Simulate this Layout, Used a linear step size while also using a parametric analysis. That gives us the 6 values.
Linear Step ADL :
![lab%204%20images/TRANS%201.JPG](lab%204%20images/TRANS%201.JPG)
Parametric Analysis:
![lab%204%20images/nmos%20parametric%20page.JPG](lab%204%20images/nmos%20parametric%20page.JPG)
2.
- A
schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV
where VGS varies from 0 to 2 V in 1 mV steps. Using a 6u/600n
width-to-length ratio.
![lab%204%20images/2%20GRAPH.JPG](lab%204%20images/2%20GRAPH.JPG)
Analog Design Environment:
![lab%204%20images/2%20TRANS.JPG](lab%204%20images/2%20TRANS.JPG)
3.
- A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
![lab%204%20images/3%20GRAPH.JPG](lab%204%20images/3%20GRAPH.JPG)
To Simulate this Layout, Used a linear step size while also using a parametric analysis. That gives us the 6 values.
Linear Step ADL :
![lab%204%20images/3%20TRANS.JPG](lab%204%20images/3%20TRANS.JPG)
Parametric Analysis:
![lab%204%20images/3%20PARAMETRIC.JPG](lab%204%20images/3%20PARAMETRIC.JPG)
4.
- A
schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV
where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n
width-to-length ratio.
![lab%204%20images/3%20SCHEMATIC.JPG](lab%204%20images/3%20SCHEMATIC.JPG)
![lab%204%20images/4%20GRAPH.JPG](lab%204%20images/4%20GRAPH.JPG)
Analog Design Environment:
![lab%204%20images/4%20TRANS.JPG](lab%204%20images/4%20TRANS.JPG)
Part 2: Lay out a 6u/0.6u NMOS and PMOS device and connect all 4 MOSFET terminals to probe pads)
Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads.
NMOS Device:
![lab%204%20images/5%20NMOS%20ZOOM.JPG](lab%204%20images/5%20NMOS%20ZOOM.JPG)
Connecting to Probe Pads:
Full
Layout View:
Extracted Layout View:
![lab%204%20images/5%20EXTRACTED.JPG](lab%204%20images/5%20EXTRACTED.JPG)
Layout Passing DRC:
![lab%204%20images/5%20NMOS%20DRC%20CONFIRMED.JPG](lab%204%20images/5%20NMOS%20DRC%20CONFIRMED.JPG)
![lab%204%20images/5%20DRC.JPG](lab%204%20images/5%20DRC.JPG)
Schematic to be Compared with Layout Using LVS:
LVS Between Schematic and Layout: LVS shows both match
![lab%204%20images/5%20FINAL%20LVS.JPG](lab%204%20images/5%20FINAL%20LVS.JPG)
Lay out a 6u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads
PMOS Device:
![lab%204%20images/6%20PMOS%20ZOOMED%20IN%20LAYOUT.JPG](lab%204%20images/6%20PMOS%20ZOOMED%20IN%20LAYOUT.JPG)
Connecting to Probe Pads:
Full
Layout View:
Extracted Layout View:
Layout Passing DRC:
![lab%204%20images/5%20DRC.JPG](lab%204%20images/5%20DRC.JPG)
Schematic to be Compared with Layout Using LVS:
LVS Between Schematic and Layout: LVS shows both match
![lab%204%20images/6%20LVS%20FINAL.JPG](lab%204%20images/6%20LVS%20FINAL.JPG)
Lab 4 Files: HERE
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