EE 421L

Lab 3  

Authored by Jeremy Morgan

Email: morgaj7@unlv.nevada.edu

Due: 9/20/2017

Pre-lab:

Finish the rest of Tutorial 1.

Lab:

Overall:
Constructed a 10k N-Well resistor using further detailed design constraints.
Utilizing the 10k N-well Resistor, constructed 10 bit DAC based on our schematic from lab2.
Compared simulations utilizing original lab 2 schematic and new 10k N-well resistor to test functionality.
 
Part 1: Setting Up 10k Resistor)

The image below shows the dimensions and calculations of the resistor layout.

 
    
Using what we learned in tutorial 1.
I constructed the calculated resistor using the dimensions.
I then extracted to show the Resistance Calculated.

N-well 10k Resistor:



Ful Resistor View:



   
Part 2: Constructing 10 bit DAC Using N-Wells)

Utilizing our 10k ohm N-Well Resistor we will be constructing a 10 bit DAC like the one created in Lab 2.

To do this, we will arrange the N-Well in the pattern of the 10bit DAC Below:



The Resistor in this graph are layed out in a Two in Series - One in Parallel pattern that we will mimic with the N-Well As seen below:
   
Layout of 10-bit DAC Using Nwells:                 Extracted View:

                                 

Mid-Level View of DAC Pattern:



   After checking for errors against DRC, we can continue: 


 
Part 3: Comparing N-Well 10 bit DAC to Lab 2 10 bit DAC)

To know if our N-Well based 10 bit DAC works properly, we will be comparing it to the 10 bit DAC we made in Lab2.
We will utilize the N-Well 10 bit DAC in simulations and compare them to the Lab 2 10 bit DAC.

First we must make sure that there is no disparities in the design between the N-Well and the Lab 2 DAC.
To do this, we will use LVS (Layour Versus Schematic) to compare the design of both and make sure there will be no errors later.

Running using Verify -> LVS Yields the following:



Our LVS was succesfull and we can continue.

Now we can begin Simulating,

We will be simulating the below circuit for Vin and Vout and comparing how the N-Well 10 bit DAC compares to the Lab 2 schematic.

Simulation:



Original simulation of Vin vs. Vout with Lab 2 Schematic:

 

We Can add our 10 bit N-well DAC to the simulation by copying the files over and editing our environment options.

From our ADL Window we can add the text "ext" (the name of our extracted view) into the switch view list
This will allow us to simulate the effects of the 10 bit N-well DAC



The new simulation yields:



Old Simulation VS. New Simulation with N-Well


The simulations are basically the same, meaning our 10 bit N-well DAC functions as theorized.

Lab 3 Zip File : Here
    

Return to EE 421L Labs