EE 421L
Lab 8
Authored
by Jeremy Morgan, Preston Donovan, Miguel Morga
Email: morgaj7@unlv.nevada.edu, donovp@unlv.nevada.edu, morga@unlv.nevada.edu
Due: 12/6/2017
Lab Description:
Generation of Test Chip
LAB 8 DIRECTORY (zip file): HERE
Overall:
Chip Contents:
2 - Course Projects (Jeremy, Preston)
1 - 31 stage ring oscillator (w/buffer)
1 - 6/.6 NMOS
1- 12/.6 PMOS
1 - NAND Gate (6/.6 NMOS - 12/.6 PMOS)
1 - NOR Gate (6/.6 NMOS - 12/.6 PMOS)
1 - XOR Gate (6/.6 NMOS - 12/.6 PMOS)
1 - Inverter (6/.6 NMOS - 12/.6 PMOS)
1 - 25k Resistor
1 - 25k / 10k Voltage Divider
1 - 100k High Res
1 - 50k High Res
1 - Bandgap
1 - XNOR Gate (6/.6 NMOS - 12/.6 PMOS)
Pin Connections:
![images/1a.JPG](images/1a.JPG)
Using Chip
Insert Chip into breadboard.
Ground is global at pin <20>. Make sure to ground. VDD is not global.
Use pin diagram above and chip diagram below to test various functions of chip (highlighted above).
Example (testing Inverter):
Ground gnd! at pin <20>
Insert VDD into pin <35>
Insert a voltage into pin <34>
Ai at pin <36> should now be inverse of pin <34>
Chip Diagram (pin locations)
![images/11.JPG](images/11.JPG)
Chip Design:
Schematic:
![images/chip_schematic.JPG](images/chip_schematic.JPG)
Layout:
![images/chip_layout.JPG](images/chip_layout.JPG)
LVS:
![images/chip_LVS.JPG](images/chip_LVS.JPG)
DRC:
![images/chip_drc.JPG](images/chip_drc.JPG)
Components of Chip:
31-Stage Ring Oscillator:
Schematic
Symbol
![images/1111ring.JPG](images/1111ring.JPG)
NAND:
Schematic
Symbol
![images/NAND_Symbol.JPG](images/NAND_Symbol.JPG)
NOR:
Schematic
Symbol
![images/NOR_SYMBOL.JPG](images/NOR_SYMBOL.JPG)
PMOS:
Schematic
Symbol
![images/PMOS_SYMBOL.JPG](images/PMOS_SYMBOL.JPG)
NMOS:
Schematic
Symbol
![images/NMOS_SYMBOL.JPG](images/NMOS_SYMBOL.JPG)
Voltage Divider (25k / 10k):
Schematic
Symbol
![images/VD_SYMBOL.JPG](images/VD_SYMBOL.JPG)
Inverter:
Schematic
Symbol
![images/INVERTER_SYMBOL.JPG](images/INVERTER_SYMBOL.JPG)
Bandgap:
Schematic
Symbol
![images/BANDGAP_SYMBOL.JPG](images/BANDGAP_SYMBOL.JPG)
XOR:
Schematic
Symbol
![images/XOR_SYMBOL.JPG](images/XOR_SYMBOL.JPG)
XNOR:
Schematic
Symbol
![images/xnor_symbol.JPG](images/xnor_symbol.JPG)
Course Project (Preston):
Schematic
Symbol
![images/PRESTON_SYMBOL.JPG](images/PRESTON_SYMBOL.JPG)
Course Project (Jeremy):
Schematic
Symbol
![images/JEREMY_SYMBOL.JPG](images/JEREMY_SYMBOL.JPG)
LAB 8 DIRECTORY (zip file): HERE
Return to EE 421L Labs