Lab

Lab Project - EE 421L

Authored by Miguel Morga,

November 14, 2017

morga@unlv.nevada.edu

Lab Description:

The first part of the project was to design an even parity checking circuit having a 9-bit input word, 8-bits data and 1-bit parity. The parity checking circuit outputs a 1 (0) when the even parity check is valid (invalid) . Parity is used as a form of error detecting in data transmission which can even be caused by noise. Parity checkers are used to ensure that the received data is accurate.

Lab Report:

Inverter:

In order to create a parity checking circuit with XOR gates, an inverter needed to be created so it can be added to the circuit. I acquired this inverter from one of my previous labs and simulated it to make sure it worked. With an input of 0, I recieved an output of 1.

Schematic	Symbol	Simulation Schematic	Simulation

Layout	Extracted

Xor Gate:

The XOR gate used in this project was also acquired from a previous lab I did and to make sure it worked I made a simulation schematic out of it and simulated it. With two inputs (A=0,B=1) the output was a 1.

Schematic	Symbol	Simulaiton Schematic	Simulation

Layout	Extracted

Even Parity Checker:

For my parity checker I used 8 XOR gates, 1 inverter, and 1 digital output pad to buffer the output before it enters a pad. The inputs to my circuit are D0-D7,P and the output is check. 8 gates are used because the outputs need to keep being fed into the next XOR gates' inputs to eventually get a single even or odd output signal. XOR gates are really easy to use for parity checkers because an even amount of inputs gives off an output of 0, and an odd amount of inputs give off an output 1. It was required for an output of 1 when an even amount of inputs is given so an inverter is needed on the last XOR gate. This with the parity bit connecting to the last XOR gate checks to see if the amount of inputs is even for an output of 1 or an odd amount of inputs for an output of 0.

Schematic	Symbol

Layout	Extracted

DRC	LVS

Simulation Schematic	Simulation

I created a simulation schematic with 8-bits, having varying periods and pulse widths. The varying pulse widths and periods made it easier for me to see the outputs at a certain point of the simulation. The simulation above shows varying results with different input bits:

Results:

[Check@V1] = (D0=1,D1=1,D2=1,D3=1,D4=1,D5=1,D6=1,D7=1,P=1) = 0 {9 Odd amount of bits including Parity bit}

[Check@V2] = (D0=0,D1=1,D2=1,D3=1,D4=1,D5=1,D6=1,D7=0,P=0) = 1 {6 Even amount of bits including Parity bit}

[Check@V3] = (D0=0,D1=0,D2=0,D3=0,D4=1,D5=1,D6=0,D7=0,P=0) = 1 {2 Even amount of bits including Parity bit}

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