Lab Project - ECE 421L 

Authored by Byron Gorsuch,

gorsuch@unlv.nevada.edu,

11/15/2017 

The purpose of this lab project is to design and layout an even parity checking circuit with a 9-bit input word. 8 bits will be input data, and the final bit will be for parity. The device will output a 1 if even parity and a 0 if odd. The inputs of the circuit will be D0-D7 and P and the output will be check.

Part One: Schematic

The parts required for this project have been created and layed out in previous labs which can be found here. The main component used to create the parity checker was the XOR gate.

A 12u/6u and a 96u/48u inverter were used in order to create a buffer for the output of the device before being placed on a pad. 96u/48u is a scale of 8 greater than 12u/6u. The buffer is used to reduce noise from the output signal.

From the above components the parity checker was created. The two input XOR gate will only output a value of 1 if there are an odd number of 1s input. Therefore the output of the cascade of gates must be inverted to create an even parity check.
XOR Truth Table A B Out 0 0 0 0 1 1 1 0 1 1 1 0

The output of the schematic should be buffered before being output onto a pad. The layout for this design was placed into and connected to a 40-pin padframe as in the schematic to the right.

Pin # Connection 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 P 10 check 20 gnd! 40 vdd!

The Two main components used to layout the design were the XOR gate and buffer. Both components were laid out using a standard cell frame in order to make laying out the entire parity chekcer easier.

By using the above layouts, the parity check layout was created.

The layout was then placed into a 40-pin padframe layout. The output of the design is buffered before being connected to the pin. The layout is verified using DRC and LVS.	Layout with padframe	Extracted view with padframe
Extracted View closeup	Successfull DRC	Successful LVS

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