Lab 06 - EE 421L 

Authored :: Aaron Escobedo,

Email :: Escoba3@UNLV.Nevada.edu 

Due :: October 25th, 2017

  

Prelab

This prelab has us complete tutorial 4 from the cmosedu.com Cadence Design Systems Tutorials

Initially, we will copy our files from tutorial 3 and create a NAND gate in a schematic form as shown below.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand2%20schematic.JPG
Nand Schematic View
http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand2%20symbol%20view.JPG
Nand Symbol View


From here, we should test our NAND gate to ensure it is working correctly - lets set up the schematic shown here.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%20simulation%20schematic.JPG
Nand Simulation Schematic
http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand2%20simulation%20results.JPG
Nand Simulation Results

These are the expected results, as with our A input always tied to Vdd (5V) and an oscillating input, we should expect the above.

Now, lets move into creating a layout for this schematic. Following the instructions from the tutorial, I was able to create a similar set up.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%20layout.JPG
Layout view of Nand gate
http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%20layout%20LVS%20passed.JPG
LVS layout - net lists match!

This completes the tutorial and prelab section.

Lab Work

We are asked to create both a NAND gate and a 2-input XOR gate, we did create the NAND gate from the Pre-Lab, and thus we must now create a XOR gate.

When we created the NAND gate in the prelab, it was incorrectly sized, and thus, we must make another one to with a 6u/.6u W/L ratio, lets begin with that

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%206_0.6%20Schematic.JPG
Notice that the W/L ratio is now 6u/.6u		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%206_0.6%20Symbol.JPG
I also created a new symbol, only initials were added


Now we will create another layout for this circuit

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Standard%20cell%20frame.JPG
A good way to start is to create a standard cell frame to place circuits on top off. 		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%206_0.6%20Layout.JPG
With the standard cell frame, we can create circuits faster.		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Nand%206_0.6%20LVS%20netlist%20match.JPG
Passed LVS

Now, we will work on creating an XOR logic gate, we can start off with the schematic and symbols shown below.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/XOR2%20schematic.JPG
XOR Schematic View
http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/XOR2%20symbol.JPG
XOR Symbol View

Next, lets build up the layout once again using standard cell frames.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/XOR_Layout.JPG
Layout of XOR Logic gate using standard cell frames		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/XOR_Layout%20LVS%20passed.JPG
A passed LVS


From here we will now simulation the XOR gate, the NAND gate, and an Inverter as we were also asked to preform this task. The NAD gate is taken from the Prelab while the inverter is taken from a previous lab.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Schematic%20for%20invert%20nand%20xor.JPG
Inverter, Nand, Xor Simulation Schematic
http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/Simulation%20results%20for%20invert%20nand%20xor.JPG
Simulation Results from Nand, Xor, and Inverter Schematic

Now that we are ensured that all of our components are working as expected, we can create a full adder circuit.

First, we will create a schematic and associated symbol for a full adder. To solve for a full adder, this is what we must first know the logic associated with a full adder - this is shown below.

ABCinSCout
00000
00110
01010
01101
10010
10101
11001
11111

From here, we can create a schematic that follows this logic, which is now shown below;

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/full%20adder%20schematic.JPG
Full adder Schematic		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/full%20adder%20symbol.JPG
Full adder symbol

Now, we can simulate a full adder circuit easier, this is shown below with the results

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/simulation%20schematic%20for%20full%20adder.JPG
Full adder simulation schematic		http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/simulation%20results%20for%20full%20adder.JPG
Full adder simulation results


Finally, you can vie wmy backed up data here

http://cmosedu.com/jbaker/courses/ee421L/f17/students/escoba3/Lab6/Images/backed%20up%20data.JPG

Link to Drive



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