Lab 05 - ECE 421L 

Authored by Aaron Escobedo

escoba3@unlv.nevada.edu

10/2/17

PreLab - Complete Tutorial 3

   
    Here is some of my data from completing the Tutorial 3

By using the copy and paste method described in the lab, I was able to create a new schematic and assocaited symbol


Following that, I create the associated Layout designs, again following the examples given in Tutorial 3

Layout View

Extracted View

Next, we need to simulate this inverter, I set up the following schematic



This produced the following results

ADE Parameters

Resulting graph from schematic

• Draft schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4

Initial Schematic (m=1)

Secondary Schematic (m=4)

Layout view of the Schematic for 12u/6u

Layout view of the Schematic for 48u/24u

Extracted View of Layout for 12u/6u

Extracted View of Layout fort 48u/24u

Passed LVS for 12u/6u Inverter

Passed LVS For 48u/24u Inverter

• Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load

100fF Load

1pF Load

10pF Load

100pF Load

Here, we can clearly see it takes more and more time to switch from a high state to a low state as the capacitor value increase. This makes sense as the value of the capacitor has a large impact on time constants within the formula;

Change in voltage = (V[final] - V[initial])(1-e^[-{t/RC}]

46u/24u Simulation

In a similar manner, I first created the following schematic;



And these are the following results from this circuit with varying capacitive loads.

100fF Load

1pF Load

10pF Load

100pF Load

• Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations 

	12u/6u Specture	12u/6u UltraSim	48u/24u Specture	48u/24u UltraSim
100fF Load
1pF Load
10pF Load
100pF Load