Lab 2 - ECE 421L 

Author :: Aaron Escobedo

Escoba3@unlv.nevada.edu

September 13th, 2017

Pre-Lab

Once I was able to download the lab2.zip files and upload them to the proper directory, as well as defining the new directory, this is the schematic that first loaded

Lab 2

Design of a 10-bit DAC using an n-well R of 10k

This design follows what was generally expected except I place a 2R valued resistor instead of 2 R sized resistors in series. 

How to create a symbol view for your design

With the above n-well constructed, we can create a symbol to make it much easier to view in a large circuit. By selecting Create -->Cellview-->From Cellview, we should get something like this;

Determining the total output resistance of the DAC

When two resistors are placed in parallel of the same value, the result will be a new total resistance of half the orginal. This idea actually works itself here as the last two resistors are 2R//2R, which would equal R. That R is in series with another R, thus again creating a 2R. This process repeats which results in the final output resistance being R alone. 

Delay, driving a load. 

If we use the formula 0.7RC to predict the delay of a DAC in this manner, we should expect the following;
R = 10kl
C = 10pF
0.7(10k)(10p) = 70ns

The following represents my schematic and simulation of this idea;





As expected, the first time constant is acheived at ~70ns

Simulations to verify your design functions correctly

Now, I will use the DAC I recreated to replace the Ideal DAC in the orginal schematic, below represents my new schematic

When I simulate this, I received the following

Which nearly represents what we saw with the ideal DAC, the difference being a start up time in the beginning of the output signal

Simulation when driving a 10k load

With this, we can clearly see a phase shift in the output voltage

Simulation with an RC Load

With this, we can see both a phase shift and a reduction in output voltage

Real Circuit considerations

In a real circuit, the resistance of the switches may not be small compared to the value of R, in such a case, the voltage on the output will be smaller as the resistance in series will be taken up more by the input resistance. 

Backing up files

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