Final_Project

Final Project - ECE 421L

Authored by Trevor Ensign

ensigt1@unlv.nevada.edu

November 15, 2017

This project involved creating a 9-bit even parity checker circuit that takes an 8-bit word and checks it with a parity bit to determine whether or not there was an error in transmitting the data.
The first part of the lab was creating an XOR gate. For my design, I made an XOR gate using 4 transistors. The B input is tied to the source of the second PMOS and to an inverter. The only problem with this technique is that when both inputs are low, the PMOS pulls the output to its threshold voltage. Fortunately, when all the XOR gates are chained together with the output buffer, it allows the check output to acheive full swing. Simulations and layout can be seen below. There is not ntap or ptap on the XOR layout because it is added in the parity layout.

XOR:

XOR Layout

http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/proj/ee421_finalproject_pics/ee421_finalproject/xor_sim.JPG

XOR No Load Sim

The second part of the project involved designing a output buffer. This buffer I used to stabilize the switching of the XOR gates so the check output acheives a full swing. I also designed a capacitor to prevent the output swinging when A and B switch. The total size of the buffer was 96/48 with a 96.96fF capacitor, which had a simulated rise time of about 39.4 ps. You can see this result in the simulation below.

Buffer:

96.96 fF Capacitor Extracted	Buffer Layout with Capacitor
Buffer Extracted View with LVS	Buffer Schematic

Buffer Delay

After I designed the buffer, I decided to use the provide output pad buffer with ESD protection provided on the CMOSedu website. The reason I designed a seperate buffer from the output pad one was because I did not want to mess up the layout that was already designed well. You can see the schematic for this output pad below.

Output Pad:

http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/proj/ee421_finalproject_pics/ee421_finalproject/output_pad.JPG

Output Pad with ESD protection

Finally, I was able to design the even parity checker. I used a total of eight XOR gates that takes an 8 input word and 1 parity bit. After the buffer was added, it gave the correct logic for the even parity check. That is, when there are an even number of high inputs, it outputs a one. When there are an odd number of high inputs, it outputs a 0. I simulated the parity checker a few different ways. The first was without a load, and then a 10pF load was added to simulate the capacitance of the scope probe tip. The simulations shown are with a clock input of 1MHz, but in my project file I also have simulations for 40MHz and 500kHz.

Even Parity Checker:

Even Parity Full Layout	Even Parity Layout Zoom
Even Parity Gate Connection Zoom	Even Parity Extracted View with LVS
Even Parity Schematic	Even Parity Simulation Schematic with Scope Capacitor
1MHz Simulation with No Scope Load	1MHz Simulation with Scope Load

You can download files for this lab here.

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