Lab 6 - EE 421L 

Authored by Trevor Ensign

ensigt1@unlv.nevada.edu
October 25, 2017    

 

In this lab we created a full adder using NAND and XOR gates.

 
http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab6/nand_layout.JPG
NAND Schematic
http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab6/nand_extracted.JPG
NAND Extracted
 
 
 

http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab6/xor_layout.JPG
XOR Layout
http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab6/xor_extract.JPG
XOR Extracted
http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab6/gatesim.JPG
Gate Schematic		http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab5/48_extract.JPG
Gate Sim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab5/48_LVS.JPG
LVS		http://cmosedu.com/jbaker/courses/ee421L/f17/students/ensigt1/lab5/48_LVS.JPG
 LVS

You can download files for this lab here.

 

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