Lab Project - ECE 421L
Back in the olden days of coding and digital processing, external noise became a major issue when trying to send data from one terminal to another. When transmitting a binary number, the external noise would occasionally flip one of the bits from a 1 to a 0 or from a 0 to a 1, making the data flawed and incorrect. Because of this regular occurance, parity bits began to be included along with the main binary code as a check for the receiver as to if the transmitted data is correct or not.
According to the usual convention, a
parity bit of 1 represents an odd
number of 1's in the data, whereas a 0 represents an even number of
1's. By comparing the parity bit to the actual number of 1's received,
the receiver would be able to tell if any of the data had been altered
during transmission.
In this project, a parity bit checker will be designed in order to compare a received parity bit with the received code to tell the receiver if the received data is correct or not.
Although there are several different standards in designing a parity bit checker, I decided to go the route of XOR gates. When looking at two bits, if both of them are 0 or both of them are 1, there is an even number of 1's in that set. If one bit is 0 and the other is 1, then there is an odd number of 1's in that set. Because of this, if two bits are fed into an XOR gate, an output of 1 means that there is an odd number of 1's in that set, whereas a 0 represents an even number of 1's. Then, XORing the outputs of the first row of XOR's shows whether that block has an even or odd number of 1's. Continuing on with this trend, the output of the final XOR gate gives what the parity bit should be for that block of data.
Once the correct value for the parity bit has been found, that value needs to be compared with the provided parity bit. Luckily, an XOR gate shows whether or not two values are equal If the output of the XOR is 1, the numbers are not equal; an output of 0 represents equality. According to the project description, an output of 1 should represent that the parity bit is correct, so the output of the equivalence checker XOR gate needs to be inverted to output the correct result.
Project Schematic and
Simulations:
Shown below is the final
circuit used for the parity checker, as well as the schematics and
symbols of the . The XOR gates used were the ones
created in lab 6, and the inverter used was the one provided in lab 7,
but the sizes of the transisters were altered to bring the switching
voltage to 2.5V,
Off of the above circuit, the following symbol was created,
The created symbol was then placed in a circuit to be used to simulate the parity bit checker, as shown below,
Then, the
following ADE
L configuration was used. The simulation time does not matter so long
as it surpasses the time delay through the 4 levels of XOR's and the
inverter,
The schematic was then simulated with 4 different sets of inputs, resulting in the following simulations,
The inputs being all zero results in an even number of 1's, so the provided parity bit of 0 is correct.
Inputting all 1's results in an even number of 1's, meaning that the provided parity bit of 1 is incorrect.
Inputting 10110100 gives an even number of 1's, meaning that the provided parity bit of 1 is incorrect.
Inputting 00110010 gives an odd number of 1's, meaning that the provided parity bit of 1 is correct.
As can be seen by the simulation results, the parity bit checker gives the correct output given multiple different sets of inputs.
Project Layout:
The above schematic was then laid out using the building blocks shown below,
XOR Inverter
The output pad used in the final schematic was the one provided on the website. Putting all of the pieces together results in the layout shown below. The individual parts of the circuit are labeled, and the original schematic with labeled components is shown below the layout,
This layout correctly DRC's and LVS's, as shown below,
All of the files associated with this lab have been backed up in Google Drive.