Lab 4 - EE 421L
Jeeno Doria
doriaj3@unlv.nevada.edu
Today's
date
9/20/2017
Lab
description: In this lab we will generate 4 schematics and simulations.
In order to start the lab we must completely go through Tutorial 2. We
will design a PMOS/NMOS layout, schematic and symbol.
Pre-Lab:
-Me going through Tutorial 2. Done NMOS
PMOS
- Back-up all of your work from the lab and the course.
-me backing up all my work from the lab and course. done
Lab:
- A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.
-VGS
and V1 are both stepping up from 0V to 5V. V1's current flow is limited
depending on VGS, so as VGS steps up, V1 can only get to the current
step of VGS, which is why the curve becomes constant near the end. 
- A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.
-I
just did what it said to do and this is what came up. The curve seems
to have increase since VSG approached the threshold voltage, which is
0.7V. The device is now working.
- A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps.
- A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
- A 6u/0.6u NMOS device with all 4 MOSFET terminals to probe pads and directly adjacent to the MOSFET (so the layout is relative small).
-In order to connect the probe pads to the NMOS, I used metal 2 to 1, then metal 2 to 3 vias.
- A corresponding schematic to LVS my layout.
- A 12u/0.6u PMOS device with all 4 MOSFET terminals to probe pads.
- A corresponding schematic to LVS my layout.
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