Lab

Lab 2 - EE 421L

Jeeno Doria

doriaj3@unlv.nevada.edu

9/5/2017

Lab description: Understand analogue to digital conversion (ADC) and digital to analog conversion (DAC). Implement n-well resistors to use a 10-bit DAC.

Pre-Lab:

Step 1: Download lab2.zip

Step 2: Extract everything onto the server into the CMOSedu folder. Open up the cds.lib file and paste

DEFINE lab2 $HOME/CMOSedu/lab2

to the very bottom of the editor and then run Cadence.

Step 3: Open the library manager and go from lab2->sim_Ideal_ADC_DAC->schematic.

Step 4: Simulate the schematic by going to Launch-> ADE L -> Load State -> Cellview -> hit OK -> then finally press the green play button.

Step 5: Play around with the background color, line thickness, and type of line.
Background Color: right click the graph (not Vin or Vout)
Line Color/Thickness/Style: double click the name or the line itself.

Our input is an analogue signal at 5 volts. The reason we see ripples for Vout is because it is being converted from ADC then back to DAC with a 10-Bit converter. The more bits it can be converted to increases the precision.

LSB is the smallest increment from a DAC output, which on our simulation is Vout. It is the smallest voltage level 1-bit can represent.

On this simulation, Vin is adjusted to have an offset voltage of 4V and an amplitude of 2V. VDD is still set to 5V, which is why we see clipping at 5V on the graph. Vout cannot exceed 5V. On the original simulation with an offset of 2.5V and amplitude of 2.5V, the reason why both waves ride along each other is because it is within range; the amplitude starts at 2.5V and cango up or down another 2.5V.

Backup: I will back up my webpages and design directory using Google Drive.

To get the least significant bit (LSB), which is the minimum voltage change on the ADC's input to see a change in the digital code, we use the formula VDD/2^N.
VDD is the voltage from its source and N represents the number of bits in the converter.

For our schematic, VDD is at 5 volts and we are working with a 10-bit converter.

Lab:

The design of a 10-bit DAC using an n-well R of 10k

Determining the output resistance of the DAC (answer: R) by combining resistors in parallel and series

Verifying the simulation results match your hand calculations
.7*R*C = .7*10K*10p= 70n

How to create a symbol view

On the Schematic Editor, hit the Create Tab ->Cell View->From Cellview... then a window pops up. You can just hit OK->OK (on the next window that pops up).

Another window will appear and it is the symbol view of the schematic chosen.

Simulations to verify my design functions correctly.

On the Library Manager copy sim_Ideal_ADC_DAC and rename it to sim2_Ideal_ADC_DAC. This copied version will be used for editting and testing our DAC. Open sim2_Ideal_ADC_DAC and delete the original DAC. After it is deleted, replace it with the DAC that was created as a symbol view.

Running a simulation of the schematic above..

Simulation with a 10K resistor load

Explain what happens if the DAC drives a 10k load?

- When there is a 10k resistor as a load, the output voltage is halved from the initial voltage. This is caused because it creates a voltage divider with the additional 10K thats within the DAC. 5V*10K/(10K+10K) = 5/2 = 2.5V.

Simulation with a 10p capacitor load

- Adding a 10p capacitor load creates a low pass filter. The capacitor smoothens the signal of Vout, which is no longer rippled and as noisy.

Simulation with a 10p capacitor and 10k resistor load.

- Adding both a 10p capacitor and 10K resistor load will combine the two distinct properties from the 2 simulations above; it will smoothen out the signal and halve the input voltage. Additionally there will be a phase shift due mainly because of the capacitor load.

Discuss what happens if the resistance of the switches isn't small compared to R.

-If the resistance of the switch isn't small compared to R, the output voltage will be lower. When the switch is closed it will combine resistance, which will be larger and consequently resistrict more current.

Explain what happens if the DAC drives a 10k load?

- When there is a 10k resistor as a load, the output voltage is halved from the initial voltage.

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