Lab 5 - ECE 421L 

Authored by Preston Donovan,

donovp1@unlv.nevada.edu

September 11, 2017

  

Prelab:

Back up work

Do Tutorial 3

Postlab:

I made a 12u/6u and a 48u/24u inverter and created a chematic, layout, and symbol for each.

Here is the layouts

Pictures/lay.PNGPictures/lay4.PNG

Here are Extracted views of these layouts

Pictures/ex.PNGPictures/ex4.PNG

Here are schematics

Pictures/sch.PNGPictures/sch4.PNG

Here are symbols

Pictures/sy.PNGPictures/sy4.PNG

 

I then LVSd and DRCd both inverters

Pictures/lvsN.PNGPictures/lvsn4.PNG

Pictures/DRC.PNGPictures/DRC4.PNG

They both pass. 

After creating these I ran simulations  driving a 100fF, 1pF, 10pF, 100pF

Starting with the 12u/6u:
 

100fFPictures/100f.PNGPictures/100fout.PNGPictures/100fout.PNG
1pFPictures/1p.PNGPictures/1pout.PNGPictures/1pout.PNG
10pFPictures/10p.PNGPictures/10pout.PNGPictures/10pout.PNG
100pFPictures/100f.PNGPictures/100pout.PNGPictures/100pout.PNG
Adding on capacitence reduced the fall time of the output. At 100pf the fall time is so large it doesnt even loose half of the starting voltage, that is becasue larger capacitors take longer to discharge.

 

And 48u/24u:

 

100fFPictures/100f4.PNGPictures/100fout4.PNGPictures/100fout4.PNG
1pFPictures/1p4.PNGPictures/1pout4.PNGPictures/1pout4.PNG
10pFPictures/10p4.PNGPictures/10pouot4.PNGPictures/10pouot4.PNG
100pFPictures/100p4.PNGPictures/100pout4.PNGPictures/100pout4.PNG

These outputs are very comparable to the 12u/6u inverter but the fall time seems to be increased even more.

 

Lab 5 zip including my Layouts and schematic files can found here

 

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