Project - ECE 421L 

Authored by Desi Battle,

battled@unlv.nevada.edu

11/14/2017

Design of an even parity checking circuit with 9 bits for input.  8 bits are used for data and the last for the parity bit.

The even parity checking circuit outputs a logic 1 when the parity check is valid and logic 0 when the check is invalid.

 

parity_schem.PNG                    

**(Note: the above schematic is used to aide in explanation, for actual implementation buses were used. (View Schematic) **
The parity checker is implemented as pictured in the above schematic. Since an xor gate outputs a logic 0 if the inputs have an even number of logic 1s anda logic 1 otherwise, even

parity checking can be done by feeding the output of one stage to the next and the taking the final output and xor-ing it with P=1 to know if the input had and even number of ones.

 

 

 

parity_symbol.PNG

Symbol created for easier instantiation and simulations

 

 

 

parity_simschem.PNG        parity_op_sim.PNG

Simulation schematic and simulation results showing when P = 1 the check output = 1 when there are and even number of 1's on the data bus and 0 otherwise. (Click here to view a Simulation of ALL possible inputs)

 

 

 

 

tfbit_sim.PNGtrbit_sim.PNG

Zoomed in photos of the simulation results shows the fall and rise times of the check output when a data bit is changed.

tf = 1.3ns and tr = 1ns (note this includes the propagation delay from the multiple stages of XOR gates.

 

 

 

 

tftrP_sim.PNG

When the P bit is changed, we see much shorter rise and fall times of tr = 270ps and tf=200ps since it is directly

connected to the final xor gate.

 

 

 

 

Summary of rise/fall times

summary.png

Looking back at the schematic, it makes sense that the rise time is longer for the single gate but the fall time is 

longer when changing a bit.  This is because when a bit is changed to set the output to 0 the first three xor gates

have to go to 1.  When a bit is changed to set the output to 1 the first three xor gates are set to zero to set the

output to 1.

 

Part (II) Layout

schemlayout.PNG

For the layout I arranged the 8 nor gates as pictured above to make routing the interconnecting wires easier

 

 

Layout_gates.PNG
Layout of the even parity circuit and DRC results

Layout_full.PNG
Above is a full photo of the layout including the buffer and bonding pad used to drive the signal off chip

extractedw_lvs.png
Extracted view show including the LVS menu and result.  Full LVS Output can be found Here

To download a copy of the library used for this lab. Click here.

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